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ltc3876 1 3876f typical application features description dual dc/dc controller for ddr power with differential vddq sensing and 50ma vtt reference the ltc ? 3876 is a complete ddr power solution, com- patible with ddr1, ddr2, ddr3 and future ddrx lower voltage standards. the ltc3876 includes vddq and vtt dc/dc controllers and a precision linear vtt reference. a differential output sense amplifier and precision internal reference combine to offer an accurate vddq supply. the vtt controller tracks the precision vttr linear reference with less than 20mv total dc error. the precision vttr reference maintains 1.2% regulation accuracy tracking one- half vddq over temperature for a 50ma reference load. the ltc3876 allows operation from 4.5v to 38v maximum at the input. the vddq output can range from 1.0v to 2.5v, with a corresponding vtt and vttr output range of 0.5v to 1.25v. voltage tracking soft-start, pgood and fault protection features are provided. ddr3 1.5v vddq/20a 0.75vtt/10a 4.5v to 14v input applications n complete ddr power solution with vtt reference n wide v in range: 4.5v to 38v, vddq: 1v to 2.5v n 0.67% vddq output voltage accuracy n vddq and vtt termination controllers n 1.2% 50ma linear vttr reference output n controlled on-time, valley current mode control n frequency programmable from 200khz to 2mhz synchronizable to external clock n t on(min) = 30ns, t off(min) = 90ns n r sense or inductor dcr current sensing n power good output voltage monitor n overvoltage protection and current limit foldback n thermally enhanced 38-pin (5mm 7mm) qfn and tssop packages n motherboard memory n servers l , lt, ltc, ltm, linear technology, opti-loop, and the linear logo are registered trademarks and hot swap and no r sense are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 5487554, 6580258, 6304066, 6476589, 6774611. efficiency/power loss vddr channel 1 15k 3876 ta01a 1000pf l2 0.47h vtt0.75v 10a db2 mt2mb2 c out4 330f 3.57k 0.1f 0.1f ltc3876 100k vttr 50ma 100k 15k v in 4.7f 0.1f l1 0.47h v in 4.5v to 14v 1.5v, 20a vddq 20k sense1 C sense1 + boost1tg1 sw1 drv cc1 intv cc db1 mt1 3.57k 30.1k 15k 0.1f bg1pgnd v outsense1 + v outsense1 C pgoodtrack/ss1 ith1 sgnd rt sense2 C sense2 + boost2 tg2 sw2 drv cc2 bg2 vttrvcc vttsns vttr ith2 run pgood mb1 1f c out1 100f c out2 330fw 2 0.1f 1000pf c in1 180f w 2 1f 15k 2.2f c out3 100f load current (a) 0.1 efficiency (%) power loss (w) 90 100 11 0 3876 ta01b 6050 40 8070 4.0 4.5 1.50.5 1.00 3.0 3.52.5 2.0 forcedcontinuous mode discontinuousmode v in = 12v vddq = 1.5v downloaded from: http:///
ltc3876 2 3876f pin configuration absolute maximum ratings input supply voltage (v in ) ......................... C0.3v to 40v boost1, boost2 voltages ....................... C0.3v to 46v sw1, sw2 voltages ...................................... C5v to 40v intv cc , drv cc1 , drv cc2 , extv cc , pgood, run, (boost1-sw1), (boost2-sw2), mode/pllin voltages ....................................................... C0.3v to 6v v outsense1 + , v outsense1 C , sense1 + , sense1 C , sense2 + , sense2 C voltages ....................... C0.6v to 6v (note 1) 13 14 15 16 top view pgnd 39 uhf package 38-lead (5mm 7mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1 ith2 vddqsns vttr vttrvcc mode/pllin clkout sgnd rt v rng1 ith1 track/ss1 v outsense1 + tg2sw2 bg2 drv cc2 extv cc intv cc pgndv in drv cc1 bg1sw1 tg1 phasmdsense2 + sense2 C cvccv rng2 vttsnsboost2 v outsense1 C sense1 + sense1 C dtr1 run pgood boost1 23 22 21 20 9 10 11 12 t jmax = 125c, ja = 34c/w exposed pad (pin 39) is pgnd, must be soldered to pcb pgnd 12 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 top view fe package 38-lead plastic tssop 3837 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 cvcc sense2 C sense2 + phasmd ith2 vddqsns vttr vttrvcc mode/pllin clkout sgnd rt v rng1 ith1 track/ss1 v outsense1 + v outsense1 C sense1 + sense1 C v rng2 vttsns boost tg2 sw2 bg2 drv cc extv cc intv cc pgndv in drv cc1 bg1sw1 tg1 boost1 pgood run dtr1 pgnd 39 t jmax = 125c, ja = 28c/w exposed pad (pin 39) is pgnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range ltc3876euhf#pbf ltc3876euhf#trpbf 3876 38-lead (5mm 7mm) plastic qfn C40c to 125c ltc3876iuhf#pbf ltc3876iuhf#trpbf 3876 38-lead (5mm 7mm) plastic qfn C40c to 125c ltc3876efe#pbf ltc3876efe#trpbf ltc3876fe 38-lead plastic tssop C40c to 125c ltc3876ife#pbf ltc3876ife#trpbf ltc3876fe 38-lead plastic tssop C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ track/ss1 voltage ..................................... C0.3v to 5v dtr1, cvcc, phasmd, rt, v rng1 , v rng2 , vttsns, vddqsns, vttr, ith1, ith2 voltages ................................ ..C0.3v to (intv cc + 0.3v) operating junction temperature range (notes 2, 3, 4) ....................................... C40c to 125c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) fe package ...................................................... 300c downloaded from: http:///
ltc3876 3 3876f electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v in = 15v unless otherwise noted. (note 3) symbol parameter conditions min typ max units main control loopv in input voltage operating range 4.5 38 v vddq(reg) vttr(reg) vttsns(reg) vddq regulated operating range vttr regulated operating range vttsns regulated operating range vddq regulates differentially with respect to v outsense1 C , vttsns and vttr regulate differentially to one-half vddq with respect to v oustsense1 C 1.00.5 0.5 2.5 1.251.25 vv v i q input dc supply current both channels enabled shutdown supply current mode/pllin = 0v, no load run1 = run2 = 0v 5000 20 a a v dfb1(reg) regulated differential feedback voltage on channel 1, vddq (v outsense1 + C v outsense1 C ) ith1 = 1.2v (note 5) t a = 25c t a = 0c to 85c t a = C40c to 125c ll 0.5985 0.5960.594 0.60.6 0.6015 0.6040.606 vv v regulated differential feedback voltage on channel 1, vddq over line, load and common mode v in = 4.5v to 38v, ith1 = 0.5v to 1.9v, v outsense1 C = 500mv (notes 5, 7) t a = 0c to 85c t a = C40c to 125c ll 0.5940.591 0.60.6 0.6060.609 vv vttsns(reg) regulated voltage error on channel 2, vttsns (referenced to vttr) ith2 = 1.4v (note 5) t a = 0c to 85c t a = C40c to 125c ll C10C15 1015 mvmv regulated voltage error on channel 2, vttsns over line, load and common mode. (referenced to vttr) v in = 4.5v to 38v, ith1 = 0.5v to 1.9v, (notes 5, 7) t a = 0c to 85c t a = C40c to 125c ll C15C20 1520 mvmv i voutsense1 + v outsense1 + input bias current v dfb1 [v outsense1 + C v outsense1 C ] = 0.6v 5 25 na i voutsense1 C v outsense1 C input bias current v dfb1 [v outsense1 + C v outsense1 C ] = 0.6v C25 C50 a i vttsns i vttsns input bias current i vttsns = 750mv 5 50 na g m(ea)1,2 error amplifier transconductance ith = 1.2v (note 3) 1.7 ms t on(min)1,2 minimum on-time v in = 38v, r t = 20k, vddsns = 1.2v, v sense C = 0.6v 30 ns t off(min)1,2 minimum off-time 90 ns current sensingv sense1(max) maximum valley current sense threshold (v sense1 + C v sense1 C ) v rng = 2v, v dfb1 = 0.57v, v sense1 C = 1.5v v rng = 0v, v dfb1 = 0.57v, v sense1 C = 1.5v v rng = intv cc , v dfb1 = 0.57v, v sense1 C = 1.5v ll l 8021 39 100 3050 120 4061 mvmv mv v sense1(min) minimum valley current sense threshold (v sense1 + C v sense1 C ) (forced continuous mode) v rng = 2v, v dfb1 = 0.63v, v sense1 C = 1.5v v rng = 0v, v dfb1 = 0.63v, v sense1 C = 1.5v v rng = intv cc , v dfb1 = 0.63v, v sense1 C = 1.5v C50C15 C25 mvmv mv v sense2(max) maximum valley current sense threshold (v sense2 + C v sense2 C ) v rng = 2v, vttsns = 0.72v, v sense2 C = 0.75v v rng = 0v, vttsns = 0.72v, v sense2 C = 0.75v v rng = intv cc , vttsns = 0.72v, v sense2 C = 0.75v ll l 8021 39 100 3050 120 4061 mvmv mv v sense2(min) minimum valley current sense threshold (v sense1 + C v sense1 C ) (forced continuous mode) v rng = 2v, vttsns = 0.78v, v sense2 C = 0.75v v rng = 0v, vttsns = 0.78v, v sense2 C = 0.75v v rng = intv cc , vttsns = 0.78v, v sense2 C = 0.75v C120 C36C60 mvmv mv i sense1,2 + sense1,2 + pins input bias current v sense + = 0.6v v sense + = 2.5v 5 1 50 2 naa i sense1,2 C sense2 C pins input bias current (internal 500k resistor to sgnd) v sense1 C = 0.6v v sense1 C = 2.5v 1.2 5 aa downloaded from: http:///
ltc3876 4 3876f symbol parameter conditions min typ max units start-up and shutdownv run(th) run pin on threshold v run rising l 1.15 1.2 1.25 v v run(hys) run pin on hysteresis v run falling from v run(th) 100 mv i run(off) run pin pull-up current when off run = sgnd 2.5 a i run(hys) run pin pull-up current hysteresis i run(hys) = i run(on) C i run(off) 10 a v uvlo(intvcc) intv cc undervoltage lockout intv cc falling intv cc rising ll 3.3 3.7 4.2 4.5 vv i track/ss soft-start pull-up current 0v < track/ss < 0.6v 1 a frequency and clock synchronizationf clkout clock output frequency (steady-state switching frequency) r t = 205k r t = 80.6k r t = 18.2k 450 200500 2000 550 khzkhz khz vtt vtt channel 2 phase (relative to channel 1) v phasmd = sgnd v phasmd = floating v phasmd = intv cc 180180 240 degdeg deg clkout clkout phase (relative to channel 1) v phasmd = sgnd v phasmd = floating v phasmd = intv cc 6090 120 degdeg deg v clkout(h) clock output voltage high pulling to intv cc v intvcc v v clkout(l) clock output voltage low pulling to sgnd 0 v v pllin(h) clock input voltage high f mode/pllin >100khz 2 v v pllin(l) clock input voltage low f mode/pllin >100khz C0.5 v r mode/pllin mode/pllin input dc resistance 600 k gate driversr tg(up)1,2 tg driver pull-up on-resistance tg high 2.5 r tg(down)1,2 tg driver pull-down on-resistance tg low 1.2 r bg(up)1 bg driver 1 pull-up on-resistance bg1 high 2.5 r bg(up)2 bg driver 2 pull-up on-resistance bg2 high 1.6 r bg(down)1,2 bg driver pull-down on-resistance bg low 0.8 t d(tg/bg)1,2 top gate off to bottom gate on delay time (n ote 6) 20 ns t d(bg/tg)1,2 bottom gate off to top gate on delay time (n ote 6) 15 ns vtt reference vttr(i vttr ) vttr load regulation (vttr(i vttr ) is measured through an internal kelvin connection to the vttr pin and is specified as the ratio (vttr(i vttr )/ vddq) C50ma < i vttr < 50ma; t a = C40c to 125c 1.5 < vddq < 2.51.0 < vddq < 1.5 ll 0.49400.4930 0.50600.5070 v/v v/v internal v cc regulator v drvcc1 internal regulated drv cc1 voltage 6v < v in < 38v 5.0 5.3 5.6 v ? v drvcc1 drv cc1 load regulation i cc = 0ma to 100ma C1.5 C3 % v extvcc(th) extv cc switchover voltage extv cc rising 4.4 4.6 4.8 v v extvcc(hys) extv cc switchover hysteresis 200 mv ? v drvcc2 extv cc to drv cc2 voltage drop v extvcc = 5v, i drvcc2 = 100ma 200 mv electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v in = 15v unless otherwise noted. (note 3) downloaded from: http:///
ltc3876 5 3876f symbol parameter conditions min typ max units pgood outputpgd ov pgood overvoltage threshold v outsense , vttsns rising, with respect to reference voltage 5 7.5 10 % pgd uv pgood undervoltage threshold v outsense , vttsns falling, with respect to reference voltage C5 C7.5 C10 % pgd hys pgood threshold hysteresis v outsense , vttsns returning to reference voltage 2.0 % v pgd(lo) pgood low voltage i pgood = 2ma 0.1 0.3 v t pgd(fall) t pgd(rise) delay from ov/uv fault to pgood falling delay from ov/uv recovery to pgood rising 5020 ss electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v in = 15v unless otherwise noted. (note 3) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formulas: ltc3876uhf: t j = t a + (p d ? 34c/w) ltc3876fe: t j = t a + (p d ? 28c/w) note 3: the ltc3876 is tested under pulsed load conditions such that t j t a . the ltc3876e is guaranteed to meet performance specifications from 0c to 85c. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3876i is guaranteed to meet performance specifications over the full C40c to 125c operating junction temperature range. the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the package thermal impedance and other environmental factors. note 4: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. the maximum rated junction temperature will be exceeded when this protection is active. continuous operation above the specified absolute maximum operating junction temperature may impair the device reliability or permanently damage the device. note 5: the ltc3876 is tested in a feedback loop that adjusts (v outsense1 + v outsense1 C ) and vttsns to achieve specified error amplifier output voltages (ith1,2).note 6: delay times are measured using 50% levels. note 7: in order to simplify the total system error computation, the regulated voltage is defined in one combined specification which includes the effects of line, load and common mode variation. the combined regulated voltage specification is tested by independently varying line, load, and common mode, which by design do not significantly affect one another. for any combination of line, load, and common mode variation, the regulated voltage should be within the limits specified that are tested in production to the following conditions: a. line: v in = 4.5v to 38v, ith = 1v, v outsense1 C = 0v b. load: v in = 15v, ith = 0.5v to 1.9v, v outsense1 C = 0v c. common mode: v in = 15v, ith = 1v, to v outsense1 C = 500mv, (ch1) downloaded from: http:///
ltc3876 6 3876f typical performance characteristics transient response vddq (discontinuous mode) transient response vtt (forced continuous mode) load step vddq (discontinuous mode) load release vddq (discontinuous mode) transient response vddq (forced continuous mode) load step vddq (forced continuous mode) load release vddq (forced continuous mode) i load 20a/div v sw 20v/div i l 20a/div 10s/div 3876 g01 load transient = 0a to 15av in = 12v v out = 1.5v figure 10 circuit, vddq channel 1 v out 50mv/div v sw 20v/div i load 20a/div i l 20a/div 5s/div 3876 g03 load release = 15a to 500mav in = 12v v out = 1.5v figure 10 circuit, vddq channel 1 v out 50mv/div i load 20a/div v sw 20v/div i l 20a/div 10s/div 3876 g04 load transient = 0a to 15av in = 12v v out = 1.5v figure 10 circuit, vddq channel 1 v out 50mv/div v sw 20v/div i load 20a/div i l 20a/div 5s/div 3876 g05 load step = 500ma to 15av in = 12v v out = 1.5v figure 10 circuit, vddq channel 1 v out 50mv/div i load 20a/div v sw 20v/div i l 20a/div 5s/div 3876 g06 load release = 15a to 500mav in = 12v v out = 1.5v figure 10 circuit, vddq channel 1 v out 50mv/div i load 20a/div v sw 20v/div v out 50mv/div i l 20a/div 10s/div 3876 g07 load transient = 0a to 15av in = 12v v out = 1.5v figure 10 circuit, vddq channel 1 i load 20a/div i l 10a/div 5s/div 3876 g09 load release = 10a to 0av in = 12v v out = 0.75v figure 10 circuit, vtt channel 2 v out 50mv/div v sw 20v/div load step vtt (forced continuous mode) load release vtt i load 20a/div v sw 20v/div v out 50mv/div i l 20a/div 5s/div 3876 g02 load step = 0a to 15av in = 12v v out = 1.5v figure 10 circuit, vddq channel 1 i load 20a/div v sw 20v/div i l 10a/div 5s/div 3876 g08 load step = 0a to 10av in = 12v v out = 0.75v figure 10 circuit, vtt channel 2 v out 50mv/div downloaded from: http:///
ltc3876 7 3876f typical performance characteristics phase relationship: phasmd = ground (forced continuous mode) phase relationship: phasmd = float (forced continuous mode) phase relationship: phasmd = intv cc (forced continuous mode) overcurrent protection(forced continuous mode) regular soft start-up(forced continuous mode) short-circuit protection(forced continuous mode) soft start-up into prebiased output overvoltage protection (forced continuous mode) output tracking (forced continuous mode) v in 5v/div vddq 500mv/div vtt 500mv/div 2ms/div 3876 g10 c ss = 10nf v in = 12v vddq = 1.5v, vtt = 0.75v figure 10 circuit track/ss 200mv/div vtt 500mv/div 1ms/div 3876 g11 css = 10nfv in = 12v vddq = 1.5v, vtt = 0.75v vddq prebiased to 0.75v vtt prebiased to 0.6v figure 10 circuit run 5v/div vddq 500mv/div track/ss 200mv/div track/ss 200mv/div vtt 500mv/div vddq 500mv/div 10ms/div 3876 g12 v in = 12v vddq = 1.5v, vtt - 0.75v figure 10 circuit 500ns/div 0 3876 g17 phasmd = float v in = 6v vddq = 1.5v, vtt = 0.75v load = 0a figure 10 circuit clkout 5v/div sw2 5v/div sw1 5v/div pllin 5v/div 90 180 500ns/div 0 3876 g18 phasmd = intv cc v in = 6v vddq = 1.5v, vtt = 0.75v load = 0a figure 10 circuit clkout 5v/div sw2 5v/div sw1 5v/div pllin 5v/div 120 240 v out 50mv/div load current 20a/div 5ms/div 3876 g13 v in = 12v vddq = 1.5vcurrent limit = 23a overload = 10a to 17.5a ficure 10 circuit, vddq channel 1 i l 10a/div 10a full current limit v out greater than half regulated setting 24a v out 1v/div 50a 0a 500s/div 3876 g14 v in = 12v vddq = 1.5vi load = 0a, short = 50a figure 10 circuit, vddq channel 1 current limitfoldback v out drops below half regulated set point i l 20a/div short- circuit trigger 1v/div c out discharge c out recharge 20s/div overvoltage created by applying a charged capacitor to v out bg stays on until v out pulled below overvoltage threshold 3876 g15 v in = 12v vddq = 1.5vi load = 0a figure 10 circuit, vddq channel 1 bg1 5v/div v out 200mv/div i l 20a/div 500ns/div 60 0 3876 g16 phasmd = gndv in = 6v vddq = 1.5v, vtt = 0.75v load = 0a figure 10 circuit clkout 5v/div sw2 5v/div sw1 5v/div pllin 5v/div 180 downloaded from: http:///
ltc3876 8 3876f typical performance characteristics clkout/switching frequency vs input voltage clkout/switching frequency vs load current clkout/switching frequency vs temperature vttr load regulation vddq = 2.5v vttr load regulation vddq = 1.5v vttr load regulation vddq = 1v output regulation vs input voltage vddq channel 1 output regulation vs load current vddq channel 1 output regulation vs temperature vddq channel 1 v in (v) 0 normalized v out (%) 0 0.1 0.2 15 25 40 3876 g19 C0.1 C0.2 510 20 30 35 v out = 1.5v i load = 5a v out normalized at v in = 15v i load (a) 0 normalized v out (%) 0 0.1 0.2 46 1 0 3876 g20 C0.1 C0.2 28 v in = 15v v out = 1.5v v out normalized at i load = 4a temperature (c) C50 normalized v out (%) C0.2C0.4 0.2 0.4 0.6 0 25 50 75 100 150 3876 g21 0 C0.6 C25 125 v in = 15v v out = 1.5v i load = 0a v out normalized at t a = 25c v in (v) 0 normalized f (%) C1 1 2 10 15 20 25 30 40 3876 g22 0 C2 53 5 v out = 1.6v i load = 5a f = 200khzfrequency normalized at v in = 15v i load (a) 0 normalized f (%) C1 1 2 46 1 0 3876 g23 0 C2 28 v in = 15v v out = 1.5v f = 200khzfrequency normalized at i load = 4a temperature (c) C50 normalized f (%) C1 1 2 0 25 50 75 100 150 3876 g24 0 C2 C25 125 v in = 15v, v out = 1.5v i load = 0a, f = 200khz frequency normalized at t a = 25c i vttr (ma) C50 vttr(i vttr )/vddq (v/v) 0.520 C25 0 50 3876 g24 0.5050.500 0.495 0.490 0.485 0.5150.510 0.480 25 C40c25c 85c 125c v in = 15v f = 400khz i vttr (ma) C50 vttr(i vttr )/vddq (v/v) 0.520 C25 0 50 3876 g26 0.5050.500 0.495 0.490 0.485 0.5150.510 0.480 25 C40c25c 85c 125c v in = 15v f = 400khz i vttr (ma) C50 vttr(i vttr )/vddq (v/v) 0.520 C25 0 50 3876 g27 0.5050.500 0.495 0.490 0.485 0.5150.510 0.480 25 C40c25c 85c 125c v in = 15v f = 400khz downloaded from: http:///
ltc3876 9 3876f typical performance characteristics run pin thresholds vs temperature run pull-up currents vs temperature track/ss pull-up current vs temperature intv cc undervoltage lockout thresholds vs temperature shutdown current into v in pin vs voltage on v in pin quiescent current into v in pin vs temperature with extv cc = 0v error amplifier transconductance vs temperature vddq current sense voltage vs ith voltage vtt current sense voltage vs ith voltage temperature (c) C50 transconductance (ms) 1.701.65 1.55 1.75 1.80 25 75 150 3876 g28 1.60 1.50 C25 0 50 100 125 vddq ch2vtt ch2 temperature (c) C50 run pin thresholds (v) 1.21.0 0.6 0.4 0.2 1.4 1.6 25 75 150 3876 g31 0.8 0 C25 0 50 100 125 switching region stand-by regionshutdown region temperature (c) C50 current (a) 1210 2 14 16 25 75 150 3876 g32 86 4 0 C25 0 50 100 125 run pin above switchingthreshold run pin below switchingthreshold temperature (c) C50 current (a) 1.101.05 0.85 1.15 1.20 25 75 150 3876 g33 1.000.95 0.90 0.80 C25 0 50 100 125 temperature (c) C50 uvlo threshold (v) 4.13.5 4.3 4.5 25 75 150 3876 g34 3.93.7 3.3 C25 0 50 100 125 uvlo release(intv cc rising) uvlo lock(intv cc falling) v in (v) 0 current (a) 3520 15 10 5 40 15 25 40 3876 g35 3025 0 510 20 30 35 130c25c C45c temperature (c) C50 quiescent current (ma) 3.1 3.73.6 3.5 3.4 3.3 3.2 3.8 25 75 150 3876 g36 3.0 C25 0 50 100 125 ith voltage (v) 0 current sense voltage (mv) 8060 20 100 120 1.2 2 3876 g29 40 0 C20C40 C60 0.4 0.8 1.6 2.4 v rng = 2v v rng = 1v v rng = 0.6v ith voltage (v) 0 current sense voltage (mv) 0 C60C90 9060 30 120 1.2 2.4 3876 g30 C30 C120 0.4 0.8 1.6 2 v rng = 2v v rng = 1v v rng = 0.6v downloaded from: http:///
ltc3876 10 3876f pin functions ith2 (pin 1/pin 5): channel 2 vtt current control threshold. this pin is the output of the error amplifier and the switching regulators compensation point. the current comparator threshold increases with this control voltage. this voltage ranges from 0v to 2.2v. ith2 has been optimized to support a symmetric range of positive and negative current by moving the zero sense voltage to 1.2v. (zero inductor valley current). vddqsns (pin 2/pin 6): vddq sense. vddqsns provides the vddq regulation reference point to the vtt differential reference resistor divider. the positive input to the vtt differential reference resistor divider is vddqsns and negative input is v outsense C . the resistor divider is connected internally between vddqsns and v outsense C and is composed of two equally sized 105k resistors in series for 210k total resistance. when vddqsns is tied to intv cc , the vttr linear reference outputs are three-stated and vttr becomes the vttsns reference input. this allows the option to tie the vttr reference input to the vttr output of a second ltc3876 in a multiphase application. vttr (pin 3/pin 7): vtt reference. vttr is the buffered output of the vtt differential reference resistor divider. vttr is specifically designed for large ddr memory systems by providing superior accuracy and load regula- tion specified for up to 50ma. connect vttr directly to the ddr memory v ref input. vttr is a high output linear reference which tracks the vtt differential reference resis- tor divider and is equal to 0.5 ? (vddqsns C v outsense C ). power is supplied through vttrvcc. internally the vttr connection is connected to vddqsns reference in order to provide kelvin sensing of vttr. the output capacitor minimum should be 2.2f. vttrvcc (pin 4/pin 8): vttr supply input for vttr reference. connect to drv cc through an rc decoupling filter of 2.2f and 1 typically. mode/pllin (pin 5/pin 9): operation mode selection or external clock synchronization input. when this pin is tied to intv cc forced continuous mode operation is selected. typing this pin to sgnd allows discontinuous mode operation on channel 1, vddq while channel 2, vtt (qfn/tssop) operates in forced continuous mode. when an external clock is applied at this pin, both channels operate in forced continuous mode and are synchronized to the external clock. channel 2 vtt operates in forced continuous mode only; permitting it to accurately track vttr when sourcing and sinking load current. clkout (pin 6/pin 10): clock output of internal clock generator. its output level swings between intv cc and sgnd. if clock input is present at the mode/pllin pin, it will be synchronized to the input clock, with phase set by the phasmd pin. if no clock is present at the mode/ pllin pin, its frequency will be set by the rt pin. to syn- chronize other controllers, clkout can be connected to their mode/pllin pins. sgnd (pin 7/pin 11): signal ground. all small-signal analog components should be connected to this ground. connect sgnd to the exposed pad and pgnd pin using a single pcb trace. rt (pin 8/pin 12): clock generator frequency program- ming pin. connect an external resistor from rt to sgnd to program the switching frequency between 200khz and 2mhz. an external clock applied to mode/pllin should be within 30% of this programmed frequency to ensure frequency lock. when the rt pin is floating, the frequency is internally set to be slightly under 200khz. v rng1 , v rng2 (pin 9, pin 34/pin 13, pin 38): current sense voltage range inputs. when programmed between 0.6v and 2v, the voltage applied to v rng1,2 is twenty times (20x) the maximum sense voltage between sense1,2 + and sense1,2 C , i.e., for either channel, (v sense + C v sense C ) = 0.5 ? v rng . if a v rng is tied to sgnd the channel operates with a maximum sense voltage of 30mv, equivalent to a v rng of 0.6v; if tied to intv cc , a maximum sense voltage of 50mv, equivalent to a v rng of 1v. do not float these pins. ith1 (pin 10/pin 14): channel 1 vddq current control threshold. this pin is the output of the error amplifier and the switching regulators compensation point. the current comparator threshold increases with this control voltage. the voltage ranges from 0v to 2.4v, with 0.8v corresponding to the zero sense voltage (zero inductor valley current). downloaded from: http:///
ltc3876 11 3876f track/ss1 (pin 11/pin 15): external tracking and soft- start input for channel 1 vddq . an internal 1a temper- ature-independent pull-up current source is connected to the track/ss1 pin. a capacitor to ground at this pin sets the ramp time to the final regulated output voltage. the ltc3876 regulates v dfb1 , the differential feedback voltages (v outsense1 + C v outsense1 C ) to the smaller of 0.6v or the voltage on the track/ss1 pin. alternatively, another voltage supply connected to this pin allows the output to track the outer supply during start-up. v outsense1 + (pin 12/pin 16): vddq differential output sense amplifier (+) input of channel 1. connect this pin to a feedback resistor divider between the positive and negative output capacitor terminals of v out1 . in nominal operation the ltc3876 will attempt to regulate the dif- ferential output voltage v out1 to 0.6v multiplied by the feedback resistor divider ratio.v outsense1 C (pin 13/pin 17): differential output sense amplifier (C) input of channel 1. connect this pin to the negative terminal of the output load capacitor. this pin is the remote ground connection for vddqsns which pro- vides the input to the vtt reference (vttr) resistor divider. sense1 + , sense2 + (pin 14, pin 37/pin 18, pin 3): differ- ential current comparator (+) input. the ith pin voltage and controlled offsets between the sense + and sense C pins set the current trip threshold. the comparator can be used for r sense sensing or inductor dcr sensing. for r sense sensing kelvin (4-wire) connect the sense + pin to the (+) terminal of r sense . for dcr sensing tie the sense + pin to the connection between the dcr sense capacitor and sense resistor connected across the inductor. sense1 C , sense2 C (pin 15, pin 36/pin 19, pin 2): dif- ferential current comparator(C) input. the comparator can be used for r sense sensing or inductor dcr sens- ing. for r sense current sensing kelvin (4-wire) connect the sense C pin to the (C) terminal of r sense . for dcr sensing tie the sense C pin to the dcr sense capacitor tied to the inductor v out node connection. these pins also function as output voltage sense pins for the top mosfet on-time adjustment. the impedance looking into these pins is different from the sense + pins because there is an additional 500k internal resistor from each of the sense C pins to sgnd. dtr1 (pin 16/pin 20): detect load transient transient for overshoot reduction. when load current suddenly drops, if voltage on this dtr pin drops below half of intv cc , the bottom gate (bg) will turn off and allow the inductor current to drop to zero faster, thus reducing the v out overshoot. (refer to load-release transient detection in the applications information section for more details.) to disable the dtr feature, simply tie the dtr pin to intv cc . run (pin 17/pin 21): run control input. an internal pro- portional-to-absolute temperature (ptat) pull-up current source (~2.5a at 25) is constantly connected to this pin. taking run below a threshold (~0.8v at 25) shuts down all bias of intv cc and drv cc and places the ltc3876 into micropower shutdown mode. allowing the run pin to rise above this threshold turns on the internal bias supply and all circuitry while forcing tg and bg off. when the run pin rises above 1.2v the tg and bg drivers are turned on and an additional 10a temperature-independent pull-up current is connected internally to the run pin. the run pin can sink up to 50a or be forced as high as 6v. pgood (pin 18/pin 22): power good indicator output. this open-drain logic output is pulled to ground when vddq goes out of a 7.5% or vtt goes out of a 10% window around the regulation point, after a 50s power-bad masking delay. returning to the regulation point, there is a much shorted delay to power good, and a hysteresis of around 15mv on both sides of the window. boost1, boost2 (pin 19, pin 32/pin 23, pin 36): boosted floating driver supply for top mosfet drivers. the (+) terminal of the bootstrap capacitor cb connects to this pin. the boost pins swings between (drv cc C v schottky ) and (v in + drv cc C v schottky ). tg1, tg2 (pin 20, pin 31/pin 24, pin 35): top gate driver outputs. the tg pins drive the gates of the top n-channel power mosfet with a voltage swing of drv cc between sw and boost. sw1, sw2 (pin 21, pin 30/pin 25, pin 34): switch node connection to inductors. voltage swings are from a di- ode voltage below ground to v in . the (C) terminal of the bootstrap capacitor, cb connects to this node. pin functions (qfn/tssop) downloaded from: http:///
ltc3876 12 3876f bg1, bg2 (pin 22, pin 29/pin 26, pin 33): bottom gate driver outputs. the bg pins drive the gates of the bottom n-channel power mosfet between pgnd and drv cc . drv cc1 , drv cc2 (pin 23, pin 28/pin 27, pin 32): sup- plies of bottom gate drivers. drv cc1 is also the output of an internal 5.3v regulator, drv cc2 is also the output of the extv cc switch. normally the two drv cc pins are shorted together on the pcb, and decoupled to pgnd with a minimum of 4.7f ceramic capacitor, c drvcc . v in (pin 24/pin 28): input voltage supply. the supply voltage can range from 4.5v to 38v. for increased noise immunity decouple this pin to sgnd with an rc filter. voltage at this pin is also used to adjust top gate on-time, therefore it is recommended to tie this pin to the main power input supply through an rc filter. pgnd (pin 25, exposed pad pin 39/pin 29, exposed pad pin 39): power ground. connect this pin as close as practical to the source of the bottom n-channel power mosfet, the (C) terminal of c drvcc and the (C) terminal of c in . connect the exposed pad and pgnd pin to sgnd pin using a single pcb trace under the ic. the exposed pad must be soldered to the circuit board for electrical and rated thermal performance. intv cc (pin 26/pin 30): supply input for internal circuitry (not including gate drivers). normally powered from the drv cc pins through a decoupling rc filter to sgnd (typi- cally 2.2 and 1f) extv cc (pin 27/pin 31): external power input. when extv cc exceeds 4.7v, an internal switch connects this pin to drv cc2 and shuts down the internal regulator so that intv cc and gate-drive power is drawn from extv cc . the v in pin still needs to be powered up but draws minimum current. vttsns (pin 33/pin 37): vtt sense, channel 2 error amplifier feedback input. kelvin-connect this pin directly to desired regulation point on the vtt supply, vttsns provides the inverting regulation feedback signal for the vtt termination supply. internally the vtt error amplifier positive input connects to the vttr output for accurate vttr reference tracking. vttsns will regulate channel 2 vtt termination supply to the differential reference voltage 0.5 ? (vddqsns C v outsense1 C ). phasmd (pin 38/pin 4): phase selector input. this pin determines the relative phases of channels and the clkout signal. with zero phase being defined as the rising edge of tg1: pulling this pin to sgnd locks tg2 to 180 and clkout to 60, connecting this pin to intv cc locks tg2 to 240 and clkout to 120 and floating this pin locks tg2 to 180 and clkout to 90. cvcc (pin 35/pin 1): connect v cc . this pin should always be connected to intv cc . pin functions (qfn/tssop) downloaded from: http:///
ltc3876 13 3876f functional diagram C + tg boost tg drv v in uvlo 1.2v bg pgnd sense + sense C track/ss bg drv en_drv 10a run sw extv cc intv cc drv cc2 drv cc1 4.7v d b drv cc c b c intvcc c drvcc c out c ss 3876 fd r fb1 r fb2 vtt channel 2 vddq channel 1 v in m t m b l r sense C + 4.2v C + 0.7v 250k start stop 250k sense C v in C + C + C + 2ato 5a ptat logic control mode/pllin one-shot timer on-time adjust i cmp i rev forcedcontinuous mode phase detector clk1clk2 to channel 2 mode/clk detect clock pll/ generator in ldo en out sd rt r t clkout pgood intv cc r pgd g m g m ea1 0.6v ++ C 1a C + C + diffamp (a = 1) ch1ch2 v rng ith dtr 1/2 intv cc to logiccontrol channel 2 ea2 load release detection ovuv ov uv delay c ith2 c ith1 intv cc v outsense1 + vddqsns vttrvcc 105k 105k drv cc vttr vttsns v outsense1 C intv cc cvcc r ith2 intv cc r ith1 intv cc +C c vttr(vcc) c vttr duplicate dashed line box for channel 2 downloaded from: http:///
ltc3876 14 3876f operation ddr operation the ltc3876 is a dual channel, current mode step-down controller designed to provide high efficiency power con- version for high power ddr memory and bus termination supplies. its unique controlled on-time architecture allows extremely low step-down ratios while maintaining a fast, constant switching frequency. the ltc3876 is a complete ddr power solution with one master run pin, track/ss input and pgood output. the run pin enables all supplies. the track/ss pin determines the vddq soft-start characteristics and vtt tracks 0.5 ? vddq. pgood monitors both vddq and vtt to ensure regulation within a 7.5% typical window. the current limit settings are set independently on both vddq and vtt channels. the vddq, vtt and clkout phase relationships are set by the phasmd pin to permit multiphase operation in high power ddr solutions which require more than one vddq or vtt channel. vddq supply the ltc3876 is designed to support any ddr applica- tion where vddq can range from 2.5v down to 1v. the ltc3876 supports high power applications by differentially regulating the vddq supply, vttr reference and vtt sup- ply. the channel 1 feedback resistor divider, vddqsns and v outsense C should be tied directly to the differential vddq regulation points. for best results these connec-tions should be routed separately and kelvin connected. vddqsns is the vddq regulation sense point or positive input and v outsense C is the remote ground sense point or negative input to the vtt differential reference resistor divider. the resistor divider is connected internally between vddqsns and v outsense C and is composed of two equally sized 105k resistors in series for 210k total resistance. vtt supply the vtt supply reference is connected internally to the output of the vttr vtt reference output. vttsns provides the inverting regulation feedback signal for the vtt ter- mination supply. kelvin-connect the vttsns pin directly to desired regulation point on the vtt supply. by sensing vttsns the channel 2 vtt supply regulates to vttr. the vtt supply operates in forced continuous mode and tracks vddq in start-up and in normal operation regardless of the mode/pllin settings. in start-up the vtt supply is enabled coincident with the vddq supply. operating the vtt supply in forced continuous allows accurate tracking in startup and under all operating conditions. vtt reference (vttr) the linear vtt reference, vttr, is specifically designed for large ddr memory systems by providing superior accuracy and load regulation for up to 50ma output load. vttr is the buffered output of the vtt differential reference resistor divider. vttr is a high output linear reference which tracks the vtt differential reference resistor divider and is equal to 0.5 ? (vddqsns C v outsense C ). connect vttr directly to the ddr memory v ref input. power is supplied through vttrvcc. internally the vttr connection is connected to vddqsns reference to provide kelvin sensing of vttr. both input and output supply decoupling is important to performance and accuracy. a 2.2f output capacitor is recommended for most typical applications. it is suggested to use no less than 1f and no more than 47f on the vttr output. the typical recommended input vttrvcc rc decoupling filter is 2.2f and 1. when vddqsns is tied to intv cc , the vttr linear reference output is three-stated and vttr becomes the vttsns reference input. this allows the option to tie the vttr reference input to the vttr output of a second ltc3876 in a multiphase application. main control loop the ltc3876 is a controlled on-time, valley current mode step-down dc/dc dual controller with two channels op- erating out of phase. each channel drives both main and synchronous n-channel mosfets. the two channels oper- ate independently where channel 1 is vddq and channel 2 is the vtt termination supply which tracks 0.5 ? vddq. the top mosfet is turned on for a time interval deter- mined by a one-shot timer. the one-shot timer or the top mosfet s on-time is controlled to maintain a fixed switch- (refer to functional diagram) downloaded from: http:///
ltc3876 15 3876f ing frequency. as the top mosfet is turned off, the bottom mosfet is turned on after a small delay. the delay, or dead time, is to avoid both top and bottom mosfets being on at the same time, causing shoot-through current from v in directly to power ground. the next switching cycle is initiated when the current comparator, i cmp , senses that inductor current falls below the trip level set by voltages at the ith and v rng pins. the bottom mosfet is turned off immediately and the top mosfet on again, restarting the one-shot timer and repeating the cycle. again in order to avoid shoot-through current, there is a small dead-time delay before the top mosfet turns on. at this moment, the inductor current hits its valley and starts to rise again. inductor current is determined by sensing the voltage between sense + and sense C , either by using an explicit resistor connected in series with the inductor or by implic- itly sensing the inductors dc resistive (dcr) voltage drop through an rc filter connected across the inductor. the trip level of the current comparator, i cmp , is proportional to the voltage at the ith pin, with a zero-current threshold corresponding to an ith of 0.8v for channel 1 and 1.2v for channel 2. the error amplifier (ea) adjusts this ith voltage by compar- ing the feedback signal to the internal reference voltage. on channel 1, the difference amplifier (da) converts the differential feedback signal (v outsense1 + C v outsense1 C ) to a single-ended input for the ea; channel?2 uses vttsns directly. output voltage is regulated so that the feedback voltage is equal to the internal reference. if the load current increases/decreases, it causes a momentary drop/rise in the differential feedback voltage relative to the reference. the ea then moves ith voltage, or inductor valley current setpoint, higher/lower until the average inductor current again matches the load current, so that the output voltage comes back to the regulated voltage. the ltc3876 features a detect transient (dtr) pin on channel 1 to detect load-release, or a transient where the load current suddenly drops, by monitoring the first derivative of the ith voltage. when detected, the bottom gate (bg) is turned off and inductor current flows through the body diode in the bottom mosfet, allowing the sw node voltage to drop below pgnd by the body diodes forward-conduction voltage. this creates a more nega- tive differential voltage (v sw C v out ) across the inductor, allowing the inductor current to drop faster to zero, thus creating less overshoot on v out . see load-release tran- sient detection in applications information for details. differential output sensing this dual controllers first channel, vddq features dif- ferential output voltage sensing. the output voltage is resistively divided externally to create a feedback voltage for the controller. the internal difference amplifier (diffamp) senses this feedback voltage with respect to the outputs remote ground reference to create a differential feedback voltage. this scheme eliminates any ground offsets be- tween local ground and remote output ground, resulting in a more accurate output voltage. channel 1 allows remote output ground deviate as much as 500mv with respect to local ground (sgnd). channel 2 vtt is referenced to vttr internally which differentially tracks 0.5 ? (vddqsns C v outsense C ). drv cc /extv cc /intv cc power drv cc1,2 are the power for the bottom mosfet drivers. normally the two drv cc pins are shorted together on the pcb, and decoupled to pgnd with a minimum 4.7f ceramic capacitor, c drvcc . the top mosfet drivers are biased from the floating bootstrap capacitors (c b ) which are recharged during each cycle through an external schottky diode when the top mosfet turns off and the sw pin swings down. the drv cc can be powered on two ways: an internal low- dropout (ldo) linear voltage regulator that is powered from v in and can output 5.3v to drv cc1 . alternatively, an internal extv cc switch (with on-resistance of around 2) can short the extv cc pin to drv cc2 . if the extv cc pin is below the extv cc switchover voltage (typically 4.7v with 200mv hysteresis, see the electrical characteristics table), then the internal 5.3v ldo is en- abled. if the extv cc pin is tied to an external voltage source greater than this extv cc switchover voltage, then the ldo is shut down and the internal extv cc switch shorts the extv cc pin to the drv cc2 pin, thereby powering drv cc operation (refer to functional diagram) downloaded from: http:///
ltc3876 16 3876f and intv cc with the external voltage source and helping to increase overall efficiency and decrease internal self heating from power dissipated in the ldo. this exter- nal power source could be the output of the step-down converter itself, given that the output is programmed to higher than 4.7v. the v in pin still needs to be powered up but now draws minimum current. power for most internal control circuitry other than gate drivers is derived from the intv cc pin. intv cc can be pow- ered from the combined drv cc pins through an external rc filter to sgnd to filter out noises due to switching. shutdown and start-up the run pin has an internal proportional-to-absolute temperature (ptat) current source (around 2.5a at 25c) to pull up the pin. taking the run pin below a certain threshold voltage (around 0.8v at 25c) shuts down all bias of intv cc and drv cc and places the ltc3876 into micropower shutdown mode with a minimum i q at the v in pin. the ltc3876s drv cc (through the internal 5.3v ldo regulator or extv cc ) and the corresponding channels internal circuitry off intv cc will be biased up when either or both run pins are pulled up above the 0.8v threshold, either by the internal pull-up current or driven directly by external voltage source such as logic gate output. no channel of the ltc3876 will start switching until the run pin is pulled up to 1.2v. when the run pin rises above 1.2v, the tg and bg drivers are enabled, and track/ss released. an additional 10a temperature- independent pull-up current is connected internally to the run pin. to turn off tg, bg and the additional 10a pull-up current, run needs to be pulled down below 1.2v by about 100mv. these built-in current and voltage hystereses prevent false jittery turn-on and turn-off due to noise. such features on the run pin allows input undervoltage lockout (uvlo) to be set up using external voltage dividers from v in . at start-up channel 1 is controlled by the voltage on the track/ss pin and channel 2 tracks 0.500 ? (vddqsns C v outsense1 C ). when the voltage on the track/ss pin is less than the 0.6v internal reference, the (differential) feedback voltage is regulated to the track/ss voltage instead of the 0.6v reference. the track/ss pin can be used to program the output voltage soft-start ramp-up time by connecting an external capacitor from a track/ss pin to signal ground. an internal temperature-independent 1a pull-up current charges this capacitor, creating a voltage ramp on the track/ss pin. as the track/ss voltage rises linearly from ground to 0.6v, the switching starts, vddq ramps up smoothly to its final value and the feedback voltage to 0.6v. track/ss will keep rising beyond 0.6v, until being clamped to around 3.7v. alternatively, the track/ss pin can be used to track an external supply like in a master slave configuration. typi- cally, this requires connecting a resistor divider from the master supply to the track/ss pin (see the applications information section). track/ss1 is pulled low internally when the correspond- ing channels run pin is pulled below the 1.2v threshold (hysteresis applies), or when intv cc or either of the drv cc1,2 pins drop below their respective undervoltage lockout (uvlo) thresholds. channel 1 vddq light load operation if the mode/pllin pin is tied to intv cc or an external clock is applied to mode/pllin, the ltc3876 will be forced to operate in continuous mode. with load current less than one-half of the full load peak-to-peak ripple, the inductor current valley can drop to zero or become negative. this allows constant-frequency operation but at the cost of low efficiency at light loads. if the mode/pllin pin is left open or connected to signal ground, channel 1 will transition into discontinuous mode operation, where a current reversal comparator (i rev ) shuts off the bottom mosfet (m b ) as the inductor cur- rent approaches zero, thus preventing negative inductor current and improving light-load efficiency. only vddq channel 1 is allowed to operate in discontinuous mode. the vtt channel 2 operates in forced continuous mode at all times independent of the mode/pllin setting. in this mode, both channel 1 switches remain off. as the output capacitor discharges by load current and the output volt- age droops lower, channel 1 ea will eventually move the ith voltage above the zero current level (0.8v) to initiate another switching cycle. operation (refer to functional diagram) downloaded from: http:///
ltc3876 17 3876f power good and fault protection the pgood pin is connected to an internal open-drain n-channel mosfet. an external resistor or current source can be used to pull this pin up to 6v (e.g., vddq/vtt or drv cc ). overvoltage or undervoltage comparators (ov, uv) turn on the mosfet and pull the pgood pin low when the feedback voltage is outside the 7.5% window of the 0.6v reference voltage. the pgood pin is also pulled low when the channels run pin is below the 1.2v threshold (hysteresis applies), or in undervoltage lockout (uvlo). note that feed- back voltage of channel 1 is sensed differentially through v outsense1 + with respect to v outsense1 C , while channel 2 is sensed through vttsns. pgood is only high when both channels are within window. when the feedback voltage of channel 1 is within the 7.5% window and channel 2 within the 10% window, the open-drain nmos is turned off and the pin is pulled up by the external source. the pgood pin will indicate power good immediately after the feedback is within the window. but when a feedback voltage of a channel goes out of the window, there is an internal 50s delay before its pgood is pulled low. in an overvoltage (ov) condition, m t is turned off and m b is turned on immediately without delay and held on until the overvoltage condition clears. foldback current limiting is provided if the output is below one-half of the regulated voltage, such as being shorted to ground. as the feedback drops below one-half of the normal regulation point approaching 0v, the internal ith clamp voltage gradually drops 2.4v to 1.3v for vddq channel 1 and 2.2v to 1.8v for vtt channel 2. this reduces the induc- tor valley current level to about one-third of its maximum value as the feedback approaches 0v. foldback current limiting is disabled at start-up. frequency selection and external clock synchronization an internal oscillator (clock generator) provides phase- interleaved internal clock signals for individual channels to lock up to. the switching frequency and phase of each switching channel is independently controlled by adjust- ing the top mosfet turn-on time (on-time) through the one-shot timer. this is achieved by sensing the phase relationship between a top mosfet turn-on signal and its internal reference clock through a phase detector. the time interval of the one-shot timer is adjusted on a cycle- by-cycle basis, so that the rising edge of the top mosfet turn-on is always trying to synchronize to the internal reference clock signal for the respective channel. the frequency of the internal oscillator can be programmed from 200khz to 2mhz by connecting a resistor, r t , from the rt pin to signal ground (sgnd). the rt pin is regulated to 1.2v internally. for applications with stringent frequency or interference requirements, an external clock source connected to the mode/pllin pin can be used to synchronize the internal clock signals through a clock phase-locked loop (clock pll). the ltc3876 operates in forced continuous mode of operation when it is synchronized to the external clock. the external clock frequency has to be within 30% of the internal oscillator frequency for successful synchroniza- tion. the clock input levels should be no less than 2v for high and no greater than 0.5v for low. the mode/ pllin pin has an internal 600k pull-down resistor. multichip operations the phasmd pin determines the relative phases between the internal reference clock signals for the two channels as well as the clkout signal, as shown in table 1. the phases tabulated are relative to zero degree (0) being defined as the rising edge of the internal reference clock signal of channel 1. the clkout signal can be used to synchronize additional power stages in a multiphase power supply solution feeding either a single high current output, or separate outputs. table 1 phasmd sgnd float intv cc vddq channel 1 0 0 0 vtt channel 2 180 180 240 clkout 60 90 120 operation (refer to functional diagram) downloaded from: http:///
ltc3876 18 3876f once the required output voltage and operating frequency have been determined, external component selection is driven by load requirement, and begins with the selec- tion of inductors and current sense method (either sense resistors r sense or inductor dcr sensing). next, power mosfets are selected. finally, input and output capaci- tors are selected. output voltage programming as shown in figure 1, external resistor dividers are used from the regulated outputs to their respective ground references to program the output voltages. on channel 1, the resistive divider is tapped by the v outsense1 + pin, and the ground reference is remotely sensed by the v outsense1 C pin, this voltage is sensed differentially. connect the vttsns pin directly to the vtt output. by regulating the tapped (differential) feedback voltages to the internal reference 0.6v, the resulting output voltages are: v(vddq) C v outsense1 C = 0.6v ? (1 + r fb2 /r fb1 ) and v(vtt) = 0.500 ? (vddq C v outsense1 C ) for example, if v out1 is programmed to 1.5v and the output ground reference is sitting at C0.5v with respect to sgnd, then the absolute value of the output will be 2.0v with respect to sgnd. the minimum (differential) output voltages are limited to the internal reference 0.6v, and the maximum are 5.5v. applications information the v outsense1 + pin is a high impedance pin with no input bias current other than leakage in the na range. the v outsense1 C pin has about 30a of current flowing out of the pin. the vttsns pin is quasi-high impedance pin with minimum bias current out of the pin. differential output sensing allows for more accurate output regulation in high power distributed systems having large line losses. figure 2 illustrates the potential variations in the power and ground lines due to parasitic elements. the variations may be exacerbated in multi-application systems with shared ground planes. without differential output sensing, these variations directly reflect as an error in the regulated output voltage. the ltc3876 channel 1s differential output sensing can correct for up to 500mv of variation in the outputs power and ground lines. the ltc3876 channel 1s differential output sensing scheme is distinct from conventional schemes where the regulated output and its ground reference are directly sensed with a difference amplifier whose output is then divided down with an external resistor divider and fed into the error amplifier input. this conventional scheme is limited by the common mode input range of the difference amplifier and typically limits differential sensing to the lower range of output voltages. the ltc3876s channel 1 allows for seamless differential output sensing by sensing the resistively divided feedback voltage differentially. this allows for differential sensing in the full output range. the difference amplifier (diffamp) of the ltc3876 has a bandwidth of 8mhz, high enough so that it will not affect main loop compensation and transient behavior. to avoid noise coupling into the feedback voltage (v outsense1 + ), the resistor dividers should be placed close to the v outsense1 + and v outsense1 C . remote output and ground traces should be routed together as a differential pair to the remote output. for best accuracy, these traces to the remote output and ground should be connected as close as possible to the desired regulation point. r fb2 v outsense1 + ltc3876 v outsense1 C c out c ff (opt) 3876 f01 v out r fb1 figure 1. setting output voltage downloaded from: http:///
ltc3876 19 3876f switching frequency programming the choice of operating frequency is a trade-off between efficiency and component size. lowering the operating fre- quency improves efficiency by reducing mosfet switching losses but requires larger inductance and/or capacitance to maintain low output ripple voltage. conversely, raising the operating frequency degrades efficiency but reduces component size. the switching frequency of the ltc3876 can be pro- grammed from 200khz to 2mhz by connecting a resistor from the rt pin to signal ground. the value of this resistor can be chosen according to: r t [k ] = 41550 fkhz ( ) ? 2.2 the overall controller system, including the clock pll and switching channels, has a synchronization range of no less than 30% around this programmed frequency. therefore, during external clock synchronization be sure that the external clock frequency is within this 30% range of the rt programmed frequency. it is advisable that the rt programmed frequency be equal the external clock for maximum synchronization margin. refer to the phase and frequency synchronization section for more details. inductor value calculation the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. a higher frequency generally results in lower efficiency because of mosfet gate charge losses. in addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. the inductor value has a direct effect on ripple current. the inductor ripple current ? i l decreases with higher inductance or frequency and increases with higher v in : i l = v out f?l ?? ? ?? ? 1? v out v in ?? ? ?? ? accepting larger values of ? i l allows the use of low induc- tances, but results in higher output voltage ripple, higher esr losses in the output capacitor, and greater core losses. a reasonable starting point for setting ripple current is ? i l = 0.4 ? i max . the maximum ? i l occurs at the maximum input voltage. to guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to: l = v out f? i l(max) ?? ? ?? ? 1? v out v in(max) ?? ? ?? ? applications information figure 2. differential output sensing used to correct line loss variations in a high power distributed system with a shared ground plane r fb1 m b r fb2 m t l c in v in c out1 c out2 3876 f02 i load other currents flowing in shared ground plane power trace parasitics v drop(pwr) + C ground trace parasitics v drop(gnd) i load ltc3876 v outsense1 + v outsense1 C downloaded from: http:///
ltc3876 20 3876f inductor core selection once the value for l is known, the type of inductor must be selected. the two basic types are iron powder and fer- rite. the iron powder types have a soft saturation curve which means they do not saturate hard like ferrites do. however, iron powder type inductors have higher core losses. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite core material saturates hard , which means that in- ductance collapses abruptly when the peak design current is exceeded. this results an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! a variety of inductors designed for high current, low volt- age applications are available from manufacturers such as sumida, panasonic, coiltronics, coilcraft, toko, vishay, pulse and wrth. current sense pins inductor current is sensed through voltage between sense + and sense C pins, the inputs of the internal current comparators. the input voltage range of the sense pins is C0.5v to 5.5v. care must be taken not to float these pins during normal operation. the sense + pins are quasi-high impedance inputs. there is no bias current into a sense + pin when its corresponding channels sense C pin ramps up from below 1.1v and stays below 1.4v. but there is a small (~1a) current flowing into a sense + pin when its corresponding sense C pin ramps down from 1.4v and stays above 1.1v. such currents also exist on sense C pins. but in addition, each sense C pin has an internal 500k resistor to sgnd. the resulted current (v out /500k) will dominate the total current flowing into the sense C pins. sense + and sense C pin currents have to be taken into account when designing either r sense or dcr inductor current sensing. current limit programming the current sense comparators maximum trip voltage between sense + and sense C (or sense voltage), when ith is clamped at its maximum, is set by the voltage ap-plied to the v rng pin and is given by: v sense(max) = 0.05v rng the valley current mode control loop does not allow the inductor current valley to exceed 0.05v rng . in practice, one should allow sufficient margin, to account for tolerance of the parts and external component values. note that ith is close to 2.4v for channel 1 and 2.2v for channel 2 when in positive current limit. an external resistive divider from intv cc can be used to set the voltage on a v rng pin between 0.6v and 2v, resulting in a maximum sense voltage between 30mv and 100mv. such wide voltage range allows for variety of applications. the v rng pin can also be tied to either sgnd or intv cc to force internal defaults. when v rng is tied to sgnd, the device has an equivalent v rng of 0.6v. when the v rng pin is tied to intv cc , the device has an equivalent v rng of 2v. r sense inductor current sensing the ltc3876 can be configured to sense the inductor currents through either low value series current sensing resistors (r sense ) or inductor dc resistance (dcr). the choice between the two current sensing schemes is largely a design trade-off between cost, power consumption and accuracy. dcr sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. however, current sensing resistors provide the most ac- curate current limits for the controller. a typical r sense inductor current sensing scheme is shown in figure 3a. the filter components (r f , c f ) need to be placed close to the ic. the positive and negative sense traces need to be routed as a differential pair close to- gether and (4-wire) kelvin connected underneath the sense resistor, as shown in figure 3b. sensing current elsewhere can effectively add parasitic inductance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. applications information downloaded from: http:///
ltc3876 21 3876f r sense is chosen based on the required maximum output current. given the maximum current, i out(max) , maximum sense voltage, v sense(max) , set by v rng , and maximum inductor ripple current ? i l(max) , the value of r sense can be chosen as: r sense = v sense(max) i out(max) ? i l(max) 2 conversely, given r sense and i out(max) , v sense(max) and thus v rng voltage can be determined from the above equa- tion. to ensure the maximum output current, sufficient margin should be built in the calculations to account for variations of ltc3876 under different operating conditions and tolerances of external components. because of possible pcb noise in the current sensing loop, the current sensing voltage ripple ? v sense = ? i l ? r sense also needs to be checked in the design to get a good signal-to-noise ratio. in general, for a reasonably good pcb layout, 10mv of ? v sense is recommended as a conservative number to start with, either for r sense or inductor dcr sensing applications. for todays highest current density solutions the value of the sense resistor can be less than 1m and the peak sense voltage can be as low as 20mv. in addition, inductor ripple currents greater than 50% with operation up to 2mhz are becoming more common. under these conditions, the voltage drop across the sense resistors parasitic inductance becomes more relevant. a small rc filter placed near the ic has been traditionally used to re- duce the effects of capacitive and inductive noise coupled in the sense traces on the pcb. a typical filter consists of two series 10 resistors connected to a parallel 1000pf capacitor, resulting in a time constant of 20ns. this same rc filter, with minor modifications, can be used to extract the resistive component of the current sense signal in the presence of parasitic inductance. for example, figure 4a illustrates the voltage waveform across a 2m sense resistor with a 2010 footprint for a 1.2v/15a converter operating at 100% load. the waveform is the superposition of a purely resistive component and a purely inductive component. it was measured using two scope probes and waveform math to obtain a differential measurement. based on additional measurements of the inductor ripple current and the on-time and off-time of the top switch, the value of the parasitic inductance was determined to be 0.5nh using the equation: esl = v esl(step) i l ? t on ?t off t on + t off where v esl(step) is the voltage step caused by the esl and shown in figure 4a, and t on and t off are top mosfet on-time and off-time respectively. if the rc time constant is chosen to be close to the parasitic inductance divided by the sense resistor (l/r), the resulting waveform looks re- sistive again, as shown in figure 4b. for applications using low v sense(max) , check the sense resistor manufacturers data sheet for information about parasitic inductance. in the absence of data, measure the voltage drop directly across the sense resistor to extract the magnitude of the esl step and use the equation above to determine the esl. however, do not over filter. keep the rc time constant less than or equal to the inductor time constant to maintain a high enough ripple voltage on v rsense . applications information figure 3a. r sense current sensing figure 3b. sense lines placement with sense resistor r f r esl r sense resistor and parasitic inductance c f t3 f esl/r s pole-zero cancellation filter components placed near sense pins r f sense + ltc3876 sense C c f 3876 f03a v out c out to sense filter,next to the controller r sense 3876 f03b downloaded from: http:///
ltc3876 22 3876f note that the sense1 C and sense2 C pins are also used for sensing the output voltage for the adjustment of top gate on time, t on . for this purpose, there is an additional internal 500k resistor from each sense C pin to sgnd, therefore there is an impedance mismatch with their cor- responding sense + pins. the voltage drop across the r f causes an offset in sense voltage. for example, with r f = 100, at v out = v sense C = 5v, the sense-voltage offset v sense(offset) = v sense C ? r f /500k = 1mv. such small offset may seem harmless for current limit, but could be significant for current reversal detection (i rev ), causing excess negative inductor current at discontinuous mode. also, at v sense(max) = 30mv, a mere 1mv offset will cause a significant shift of zero-current ith voltage by (2.4v C 0.8v) ? 1mv/30mv = 53mv. too much shift may not allow the output voltage to return to its regulated value after the output is shorted due to ith foldback. therefore, when a larger filter resistor r f value is used, it is recommended to use an external 500k resistor from each sense + pin to sgnd, to balance the internal 500k resistor at its corresponding sense C pin. the previous discussion generally applies to high density/high current applications where i out(max) > 10a and low inductor values are used. for applications where i out(max) < 10a, set r f to 10 and c f to 1000pf. this will provide a good starting point.the filter components need to be placed close to the ic. the positive and negative sense traces need to be routed as a differential pair and kelvin (4-wire) connected to the sense resistor. dcr inductor current sensing for applications requiring higher efficiency at high load currents, the ltc3876 is capable of sensing the voltage drop across the inductor dcr, as shown in figure 5. the dcr of the inductor represents the small amount of dc winding resistance, which can be less than 1m for todays low value, high current inductors. in a high current application requiring such an inductor, conduction loss through a sense resistor would cost several points of efficiency compared to dcr sensing. the inductor dcr is sensed by connecting an rc filter across the inductor. this filter typically consists of one or two resistors (r1 and r2) and one capacitor (c1) as shown in figure 5. if the external (r1||r2) ? c1 time constant is chosen to be exactly equal to the l/dcr time constant, the voltage drop across the external capacitor is equal to the voltage drop across the inductor dcr multiplied by r2/ (r1 + r2). therefore, r2 may be used to scale the voltage across the sense terminals when the dcr is greater than applications information 500ns/div v sense 20mv/div 3876 f04a v esl(step) 500ns/div v sense 20mv/div 3876 f04b figure 4a. voltage waveform measured directly across the sense resistor figure 4b. voltage waveform measured after the sense resistor filter. c f = 1000pf, r f = 100 r1 r2 (opt) dcr l inductor l/dcr = (r1||r2) c1 c1 near sense pins sense + ltc3876 sense C c1 3876 f05 v out c out figure 5. dcr current sensing downloaded from: http:///
ltc3876 23 3876f the target sense resistance. with the ability to program current limit through the v rng pin, r2 may be optional. c1 is usually selected in the range of 0.01f to 0.47f. this forces r1||r2 to around 2k to 4k, reducing error that might have been caused by the sense pins input bias currents. resistor r1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. capacitor c1 should be placed close to the ic pins. the first step in designing dcr current sensing is to determine the dcr of the inductor. where provided, use the manufacturers maximum value, usually given at 25c. increase this value to account for the temperature coef- ficient of resistance, which is approximately 0.4%/c. a conservative value for inductor temperature t l is 100c. the dcr of the inductor can also be measured using a good rlc meter, but the dcr tolerance is not always the same and varies with temperature; consult the manufacturers data sheets for detailed information. from the dcr value, v sense(max) is easily calculated as: v sense(max) = dcr max(25 c) ?1 + 0.4% t l(max) ?25 c () ?? ?? ?i out(max) ? i l 2 ?? ? ?? ? if v sense(max) is within the maximum sense voltage (30mv to 100mv) of the ltc3876 as programmed by the v rng pin, then the rc filter only needs r1. if v sense(max) is higher, then r2 may be used to scale down the maximum sense voltage so that it falls within range. the maximum power loss in r1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: p loss r1 () = v in(max) ?v out () ?v out r1 ensure that r1 has a power rating higher than this value. if high efficiency is necessary at light loads, consider this power loss when deciding whether to use dcr sensing or r sense sensing. light load power loss can be modestly higher with a dcr network than with a sense resistor due to the extra switching losses incurred through r1. however, dcr sensing eliminates a sense resistor, reduces conduc- tion losses and provides higher efficiency at heavy loads. peak efficiency is about the same with either method. to maintain a good signal-to-noise ratio for the current sense signal, start with a ? v sense of 10mv. for a dcr sensing application, the actual ripple voltage will be de-termined by: v sense = v in ?v out r1? c1 ? v out v in ?f power mosfet selection two external n-channel power mosfets must be selected for each channel of the ltc3876 controller: one for the top (main) switch and one for the bottom (synchronous) switch. the gate drive levels are set by the drv cc voltage. this voltage is typically 5.3v. pay close attention to the bv dss specification for the mosfets as well; most of the logic-level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on- resistance, r ds(on) , miller capacitance, c miller , input voltage and maximum output current. miller capacitance, c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers data sheet. c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat, divided by the specified v ds test voltage. when the ic is operating in continuous mode, the duty cycles for the top and bottom mosfets are given by: d top = v out v in d bot = 1? v out v in applications information downloaded from: http:///
ltc3876 24 3876f the mosfet power dissipations at maximum output current are given by: p top = d top ?i out(max) 2 ?r ds(on)(max) 1 + () + v in 2 ? i out(max) 2 ?? ? ?? ? ?c miller r tg(hi) v drvcc ?v miller + r tg(lo) v miller ?? ? ?? ? ?f p bot = d bot ? i out(max) 2 ? r ds(on)(max) ? (1 + ) where is the temperature dependency of r ds(on) , r tg(hi) is the tg pull-up resistance, and r tg(lo) is the tg pull- down resistance. v miller is the miller effect v gs voltage and is taken graphically from the mosfet s data sheet. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transition losses, which are highest at high input voltages. for v in < 20v, the high current efficiency generally improves with larger mosfets, while for v in > 20v, the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during short-circuit when the synchronous switch is on close to 100% of the period. the term (1 + ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve in the power mosfet data sheet. for low voltage mosfets, 0.5% per degree (c) can be used to estimate as an approximation of percentage change of r ds(on) : = 0.005/c ? (t j C t a ) where t j is estimated junction temperature of the mosfet and t a is ambient temperature. c in selection in continuous mode, the source current of the top n-channel mosfet is a square wave of duty cycle v out / v in . to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the worst-case rms current occurs by assuming a single-phase application. the maximum rms capacitor current is given by: i rms ? i out(max) ? v out v in ? v in v out ?1 this formula has a maximum at v in = 2v out , where i rms = i out(max) /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. due to the high operating frequency of the ltc3876, additional ceramic capacitors should also be used in parallel for c in close to the ic and power switches to bypass the high frequency switching noises. typically multiple x5r or x7r ceramic capacitors are put in parallel with either conductive-polymer or aluminum-electrolytic types of bulk capacitors. because of its low esr, the ce- ramic capacitors will take most of the rms ripple current. vendors do not consistently specify the ripple current rating for ceramics, but ceramics could also fail due to excessive ripple current. always consult the manufacturer if there is any question. figure 6 represents a simplified circuit model for calculat- ing the ripple currents in each of these capacitors. the input inductance (l in ) between the input source and the input of the converter will affect the ripple current through applications information + + C l in 1h esr (bulk) v in esl (bulk) c in(bulk) esr (ceramic) esl (ceramic) i pulse(phase1) c in(ceramic) i pulse(phase2) 3876 f06 figure 6. circuit model for input capacitor ripple current simulation downloaded from: http:///
ltc3876 25 3876f the capacitors. a lower input inductance will result in less ripple current through the input capacitors since more ripple current will now be flowing out of the input source. for simulating positive output current loading using this model, look at the ripple current during steady-state for the case where one phase is fully loaded and the other is not loaded. this will in general be the worst-case for ripple current since the ripple current from one phase will not be cancelled by ripple current from the other phase. the ltc3876 is more complex than this example because the vtt channel can provide significant negative current. for the ltc3876 steady state worst-case, look at the condition where vddq channel is fully loaded and the vtt channel is supplying maximum negative current. this will in general be the worst-case for ripple current since the ripple current from vtt will add with ripple cur- rent from vddq when the vtt channel sinks or provides negative current. note that the bulk capacitor also has to be chosen for rms rating with ample margin beyond its rms current per simulation with the circuit model provided. for a lower v in range, a conductive-polymer type (such as sanyo os-con) can be used for its higher ripple current rating and lower esr. for a wide v in range that also require higher voltage rating, aluminum-electrolytic capacitors are more attractive since it can provide a larger capacitance for more damping. an aluminum-electrolytic capacitor with a ripple current rating that is high enough to handle all of the ripple current by itself will be very large. but when in parallel with ceramics, an aluminum-electrolytic capacitor will take a much smaller portion of the rms ripple current due to its high esr. however, it is crucial that the ripple current through the aluminum-electrolytic capacitor should not exceed its rating since this will produce significant heat, which will cause the electrolyte inside the capacitor to dry over time and its capacitance to go down and esr to go up. while it is always safest to choose the input capacitors rms rating according to the worst-case single-phase ap- plication with negative vtt current as discussed above, it is likely not necessary. for ddr memory, the vtt output load current will statistically approach zero and should never operate at sustained negative current for any significant period of time in normal operation. there could be ddr test conditions which do exercise such extremes, but again this should not be continuous. therefore, determine the worst-case rms requirement for the input capacitors and reduce as appropriate for sufficient margin. the v in sources of the top mosfets should be placed close to each other and share common c in (s). separating the sources and c in may produce undesirable voltage and current resonances at v in . a small (0.1f to 1f) bypass capacitor between the ics v in pin and ground, placed close to the ic, is suggested. a 2.2 to 10 resistor placed between c in and the v in pin is also recommended as it provides further isolation from switching noise of the two channels. c out selection the selection of output capacitance c out is primarily determined by the effective series resistance, esr, to minimize voltage ripple. the output voltage ripple ? v out , in continuous mode is determined by: v out ? i l r esr + 1 8?f?c out ?? ? ?? ? where f is operating frequency, and ? i l is ripple current in the inductor. the output ripple is highest at maximum input voltage since ? i l increases with input voltage. typi- cally, once the esr requirement for c out has been met, the rms current rating generally far exceeds that required from ripple current. in single-output applications, for the same reason that ltc3876 is only truly phase interleaved at steady state, ripple current of individual channels could add up in transient, it is advisable to consider using the worst-case ? i l , i.e., the sum of the ? i l of all individual channels, in the calculation of ? v out . the choice of using smaller output capacitance increases the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low esr to maintain the ripple voltage. applications information downloaded from: http:///
ltc3876 26 3876f multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount pack- ages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long-term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezo- electric effects. the high-q of ceramic capacitors with trace inductance can also lead to significant ringing. when used as input capacitors, care must be taken to ensure that ring- ing from inrush currents and switching does not pose an overvoltage hazard to the power switches and controller. for high switching frequencies, reducing output ripple and better emi filtering may require small value capacitors that have low esl (and correspondingly higher self-resonant frequencies) to be placed in parallel with larger value capacitors that have higher esl. this will ensure good noise and emi filtering in the entire frequency spectrum of interest. even though ceramic capacitors generally have good high frequency performance, small ceramic capacitors may still have to be parallel connected with large ones to optimize performance. high performance through-hole capacitors may also be used, but an additional ceramic capacitor in parallel is recommended to reduce the effect of their lead inductance. remember also to place high frequency decoupling capaci- tors as close as possible to the power pins of the load. top mosfet driver supply (c b , d b ) an external bootstrap capacitor, c b , connected to the boost pin supplies the gate drive voltage for the topside mosfet. this capacitor is charged through diode d b from drv cc when the switch node is low. when the top mosfet turns on, the switch node rises to v in and the boost pin rises to approximately v in + intv cc . the boost capacitor needs to store approximately 100 times the gate charge required by the top mosfet. in most applications a 0.1f to 0.47f, x5r or x7r dielectric capacitor is adequate. it is recommended that the boost capacitor be no larger than 10% of the drv cc capacitor, c drvcc , to ensure that the c drvcc can supply the upper mosfet gate charge and boost capacitor under all operating conditions. vari- able frequency in response to load steps offers superior transient performance but requires higher instantaneous gate drive. gate charge demands are greatest in high frequency low duty factor applications under high load steps and at start-up. drv cc regulator and extv cc power the ltc3876 features a pmos low dropout (ldo) linear regulator that supplies power to drv cc from the v in supply. the ldo regulates its output at the drv cc1 pin to 5.3v. the ldo can supply a maximum current of 100ma and must be bypassed to ground with a minimum of 4.7f ceramic capacitor. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers and to minimize interaction between the channels. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi- mum junction temperature rating for the ltc3876 to be exceeded, especially if the ldo is active and provides drv cc . power dissipation for the ic in this case is high- est and is approximately equal to v in ? i drvcc . the gate charge current is dependent on operating frequency as discussed in the efficiency considerations section. the junction temperature can be estimated by using the equa- tion given in note 2 of the electrical characteristics. for example, when using the ldo, ltc3876s drv cc current is limited to less than 52ma from a 38v supply at t a = 70c in the fe package: t j = 70c + (52ma)(38v)(28c/w) = 125c to prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode at maximum v in . applications information downloaded from: http:///
ltc3876 27 3876f when the voltage applied to the extv cc pin rises above 4.7v, the v in ldo is turned off and the extv cc is connected to drv cc2 pin with an internal switch. this switch remains on as long as the voltage applied to extv cc remains above 4.5v. using extv cc allows the mosfet driver and control power to be derived from the ltc3876s switching regulator output v out during normal operation and from the ldo when the output is out of regulation (e.g., start- up, short-circuit). if more current is required through the extv cc than is specified, an external schottky diode can be added between the extv cc and drv cc pins. do not apply more than 6v to the extv cc pin and make sure that extv cc is less than v in . significant efficiency and thermal gains can be realized by powering drv cc from the switching converter output, since the v in current resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(switcher efficiency). tying the extv cc pin to a 5v supply reduces the junction temperature in the previous example from 125c to: t j = 70c + (52ma)(5v)(28c/w) = 77c however, for 3.3v and other low voltage outputs, ad- ditional circuitry is required to derive drv cc power from the converter output.the following list summarizes the four possible connec- tions for extv cc : 1. extv cc left open (or grounded). this will cause intv cc to be powered from the internal 5.3v ldo resulting in an efficiency penalty of up to 10% at high input voltages. 2. extv cc connected directly to switching converter output v out > 4.7v. this provides the highest efficiency. 3. extv cc connected to an external supply. if a 4.7v or greater external supply is available, it may be used to power extv cc providing that the external supply is sufficient for mosfet gate drive requirements. 4. extv cc connected to an output-derived boost network. for 3.3v and other low voltage converters, efficiency gains can still be realized by connecting extv cc to an output-derived voltage that has been boosted to greater than 4.7v. for applications where the main input power never exceeds 5.3v, tie the drv cc1 and drv cc2 pins to the v in input through a small resistor, (such as 1 to 2) as shown in figure 7 to minimize the voltage drop caused by the gate charge current. this will override the ldo and will prevent drv cc from dropping too low due to the dropout voltage. make sure the drv cc voltage exceeds the r ds(on) test voltage for the external mosfet which is typically at 4.5v for logic-level devices. applications information figure 7. setup for v in 5.3v input undervoltage lockout (uvlo) the ltc3876 has two functions that help protect the con- troller in case of input undervoltage conditions. an internal uvlo comparator constantly monitors the intv cc and drv cc voltages to ensure that adequate voltages are pres- ent. the comparator enables internal uvlo signal, which locks out the switching action of both channels, until the intv cc and dr vcc1,2 pins are all above their respective uvlo thresholds. the rising threshold (to release uvlo) of the intv cc is typically 4.2v, with 0.5v falling hysteresis (to re-enable uvlo). the uvlo thresholds for dr vcc1,2 are lower than that of intv cc but higher than typical threshold voltages of power mosfets, to prevent them from turning on without sufficient gate drive voltages. generally for v in > 6v, a uvlo can be set through monitoring the v in supply by using external voltage dividers at the run pins from v in to sgnd. to design the voltage divider, note that both run pins have two levels of threshold voltages. the precision gate-drive-enable threshold voltage of 1.2v drv cc2 ltc3876 drv cc1 c drvcc r drvcc 3876 f07 v in c in downloaded from: http:///
ltc3876 28 3876f can be used to set a v in to turn on a channels switching. if resistor dividers are used on both run pins, when v in is low enough and both run pins are pulled below the ~0.8v threshold, the part will shut down all bias of intv cc and drv cc and be put in micropower shutdown mode. the run pins bias currents depend on the run voltages. the bias current changes should be taken into account when designing the external voltage divider uvlo circuit. an internal proportional-to-absolute-temperature ( ptat) pull-up current source (~2.5a at 25c) is constantly con- nected to this pin. when a run pin rises above 1.2v, the corresponding channels tg and bg drives are turned on and an additional 4a temperature-independent pull-up current is connected internally to the run pin. pulling the run pin to fall below 1.2v by more than an 80mv hyster- esis turns off tg and bg of the corresponding channel, and the additional 10a pull-up current is disconnected. as voltage on a run pin increases, typically beyond 3v, its bias current will start to reverse direction and flow into the run pin. keep in mind that neither of the run pins can sink more than 50a; even if a run pin may slightly exceed 6v when sinking 50a, a run pin should never be forced to higher than 6v by a low impedance voltage source to prevent faulty conditions. soft-start and tracking the ltc3876 has the ability to either soft-start by itself with a capacitor or track the output of another channel or an external supply. note that the soft-start or tracking features are achieved not by limiting the maximum output current of the controller, but by controlling the output ramp voltage according to the ramp rate on the track/ss pin. when channel 1 is configured to soft-start by itself, a capaci- tor should be connected to its track/ss pin. track/ss is pulled low until the run pin voltage exceeds 1.2v and uvlo is released, at which point an internal current of 1a charges the soft-start capacitor, c ss , connected to the track/ss pin. current-limit foldback is disabled during this phase to ensure smooth soft-start or tracking. the soft-start or tracking range is defined to be the voltage range from 0v to 0.6v on the track/ss pin. the total soft-start time can be calculated as: t ss (sec) = 0.6(v)? c ss (f) 1(a) when one particular channel is configured to track an external supply, a voltage divider can be used from the external supply to the track/ss pin to scale the ramp rate appropriately. two common implementations are co- incidental tracking and ratiometric tracking. for coincident tracking, make the divider ratio from the external supply the same as the divider ratio for the differential feedback voltage. ratiometric tracking could be achieved by using a different ratio than the differential feedback. note that the 1a soft-start capacitor charging current is still flowing, producing a small offset error. to minimize this error, select the tracking resistive divider values to be small enough to make this offset error negligible. the ltc3876 allows the user to program how channel 1 vddq tracks an external power supply. channel 2 vtt will always track vddq and be equal to 0.5 ? vddq. by selecting different resistors, the ltc3876 can achieve different modes of tracking including the two in figure 8a. to implement the coincident tracking, connect an additional resistive divider to the external power supply and connect its midpoint to the track/ss pin of the slave channel. the ratio of this divider should be the same as that of the slave channels feedback divider shown in figure 8b. in this tracking mode, the external power supply must be set higher than vddq. to implement the ratiometric tracking, the master channels feedback divider can be also used to provide track/ss voltage for the slave channel, since the additional divider, if used, should be of the same ratio as the master channels feedback divider. applications information downloaded from: http:///
ltc3876 29 3876f so which mode should be programmed? while either mode satisfies most practical applications, some trade- offs exist. the ratiometric mode saves a pair of resistors, but the coincident mode offers better output regulation. when the master channels output experiences dynamic excursion (under load transient, for example), the slave channel output will be affected as well. for better output regulation, use the coincident tracking mode instead of ratiometric. phase and frequency synchronization for applications that require better control of emi and switching noise or have special synchronization needs, the ltc3876 can synchronize the turn-on of the top mosfet to an external clock signal applied to the mode/pllin pin. the applied clock signal needs to be within 30% of the rt programmed frequency to ensure proper frequency and phase lock. the clock signal levels should generally comply to v pllin(h) > 2v and v pllin(l) < 0.5v. the mode/ pllin pin has an internal 600k pull-down resistor to ensure discontinuous current mode operation if the pin is left open. the ltc3876 uses the voltages on v in and v out pins as well as r t to adjust the top gate on-time in order to maintain phase and frequency lock for wide ranges of v in , v out and r t -programmed switching frequency f: t on v out v in ?f applications information figure 8a. two different modes of output tracking figure 8b. setup for coincident and ratiometric tracking time coincident tracking externalpower supply vddq output voltage externalpower supply vddq time 3876 f08a ratiometric tracking output voltage coincident tracking setup r fb2(1) r fb1(1) r fb2(1) r fb1(1) tov outsense1 + pin tov outsense1 C pin to track/ss1 pin external power supply vddq ratiometric tracking setup r2r1 to track/ss1 pin external power supply r fb2(2) vddq r fb1(2) 3876 f08b to v outsense1 + pin to v outsense1 C pin downloaded from: http:///
ltc3876 30 3876f as the on-time is a function of the switching regulators output voltage, this output is measured by the v out pin to set the required on-time. simply connecting v out to the regulators local output point is preferable for most applications, as the remotely regulated output point could be significantly different from the local output point due to line losses, and local output versus local ground is typically the v out required for the calculation of t on . however, there could be circumstances where this v out programmed on-time differs significantly different from the on-time required in order to maintain frequency and phase lock. for example, lower efficiencies in the switching regulator can cause the required on-time to be substantially higher than the internally set on-time (see efficiency considerations). if a regulated v out is relatively low, proportionally there could be significant error caused by the difference between the local ground and remote ground, due to other currents flowing through the shared ground plane. during dynamic transient conditions either in the line voltage or load current (e.g., load step or release), the top switch will turn on more or less frequently in response to achieve faster transient response. this is the benefit of the ltc3876s controlled on-time, valley current mode architecture. however, this process may understandably lose phase and even frequency lock momentarily. for relatively slow changes, phase and frequency lock can still be maintained. for large load current steps with fast slew rates, phase lock will be lost until the system returns back to a steady-state condition (see figure 9). it may take up to several hundred microseconds to fully resume the phase lock, but the frequency lock generally recovers quickly, long before phase lock does. for light load conditions, the phase and frequency syn- chronization depends on the mode/pllin pin setting. if the external clock is applied, synchronization will be active and switching in continuous mode. if mode/pllin is tied to intv cc , it will operate in forced continuous mode at the r t -programmed frequency. if the mode/pllin pin is tied to sgnd, the ltc3876 will operate in discontinuous mode at light load and switch into continuous conduction at the r t programmed frequency as load increases. the tg on-time during discontinuous conduction is intentionally slightly extended (approximately 1.2 times the continuous conduction on-time as calculated from v in , v out and f) to create hysteresis at the load-current boundary of continu- ous/discontinuous conduction. applications information figure 9. phase and frequency locking behavior during transient conditions phase and frequency lock lost due to fast load step frequency restored quickly phase and frequency lock lost due to fast load step frequency restored quickly phase lock resumed 3876 f09 phase and frequency locked i load clock input sw v out downloaded from: http:///
ltc3876 31 3876f if an application requires very low (approaching minimum) on-time, the system may not be able to maintain its full frequency synchronization range. getting closer to mini- mum on-time, it may even lose phase/frequency lock at no load or light load conditions, under which the sw on-time is effectively longer than tg on-time due to tg/bg dead times. this is discussed further under minimum on-time, minimum off-time and dropout operation. minimum on-time, minimum off-time and dropout operation the minimum on-time is the smallest duration that ltc3876s tg (top gate) pin can be in high or on state. it has dependency on the operating conditions of the switching regulator, and is a function of voltages on the v in and v out pins, as well as the value of external resistor r t . a minimum on-time of 30ns can be achieved when the v out pin is tied to its minimum value of 0.6v while the v in is tied to its maximum value of 38v. for larger values of v out and/or smaller values of v in , the minimum achievable on-time will be longer. the valley mode control architecture allows low on-time, making the ltc3876 suitable for high step-down ratio applications. the effective on-time, as determined by the sw node pulse width, can be different from this tg on-time, as it also depends on external components, as well as loading conditions of the switching regulator. one of the factors that contributes to this discrepancy is the characteristics of the power mosfets. for example, if the top power mosfets turn-on delay is much smaller than the turn-off delay, the effective on-time will be longer than the tg on-time, limiting the effective minimum on-time to a larger value. light-load operation, in forced continuous mode, will further elongate the effective on-time due to the dead times between the on states of tg and bg, as shown in figure 10. during the dead time from bg turn-off to tg turn-on, the inductor current flows in the reverse direction, charging the sw node high before the tg actually turns on. the reverse current is typically small, causing a slow rising edge. on the falling edge, after the top fet turns off and before the bottom fet turns on, the sw node lingers high for a longer duration due to a smaller peak inductor current available in light load to pull the sw node low. as a result of the sluggish sw node rising and falling edges, the effective on-time is extended and not fully controlled by the tg on-time. closer to minimum on-time, this may cause some phase jitter to appear at light load. as load current increase, the edges become sharper, and the phase locking behavior improves. the minimum on-time of the vtt channel is further limited by the fact that it must support negative current operation. both the tg to bg and bg to tg dead-time delays add applications information figure 10. light loading on-time extension for forced continuous mode operation dead-time delays negative inductor current in fcm during bg-tg dead time, negative inductor current will flow through top mosfets body diode to precharge sw node 3876 f10 tg-sw (v gs of top mosfet) bg (v gs of bottom mosfet) i l sw 0 v in + C i l v in l sw during tg-bg dead time, the rate of sw node discharge will depend on the capacitance on the sw node and inductor current magnitude l total capacitance on the sw node i l downloaded from: http:///
ltc3876 32 3876f to the minimum on-time of 30ns as shown in figure 10. each of the dead times are in the order of 35ns. therefore, the vtt channel minimum on time should be no less than 100ns with 150ns preferred. in continuous mode operation, the minimum on-time limit imposes a minimum duty cycle of: d min = f ? t on(min) where t on(min) is the effective minimum on-time for the switching regulator. as the equation shows, reducing the operating frequency will alleviate the minimum duty cycle constraint. if the minimum on-time that ltc3876 can provide is longer than the on-time required by the duty cycle to maintain the switching frequency, the switching frequency will have to decrease to maintain the duty cycle, but the output voltage will still remain in regulation. this is generally more preferable to skipping cycles and causing larger ripple at the output, which is typically seen in fixed frequency switching regulators. for applications that require relatively low on-time, proper caution has to be taken when choosing the power mosfet. if the gate of the mosfet is not able to fully turn on due to insufficient on-time, there could be significant heat dis- sipation and efficiency loss as a result of larger r ds(on) . this may even cause early failure of the power mosfet. the minimum off-time is the smallest duration of time that the tg pin can be turned low and then immediately turned back high. this minimum off-time includes the time to turn on the bg (bottom gate) and turn it back off, plus the dead-time delays from tg off to bg on and from bg off to tg on. the minimum off-time that the ltc3876 can achieve is 90ns. the effective minimum off-time of the switching regulator, or the shortest period of time that the sw node can stay low, can be different from this minimum off-time. the main factor impacting the effective minimum off-time is the top and bottom power mosfets electrical characteristics, such as qg and turn-on/off delays. these characteristics can either extend or shorten the sw nodes effective minimum off-time. large size (high qg) power mosfets generally tend to increase the effective minimum off-time due to longer gate charging and discharging times. on the other hand, imbalances in turn-on and turn-off delays could reduce the effective minimum off-time. the minimum off-time limit imposes a maximum duty cycle of: d max = 1 C f ? t off(min) where t off(min) is the effective minimum off-time of the switching regulator. reducing the operating frequency can alleviate the maximum duty cycle constraint. if the maximum duty cycle is reached, due to a drooping input voltage for example, the output will drop out of regulation. the minimum input voltage to avoid dropout is: v in(min) = v out d max at the onset of drop-out, there is a region of v in of about 500mv that generates two discrete off-times, one being the minimum off time and the other being an off-time that is about 40ns to 60ns longer than the minimum off-time. this secondary off-time is due to the extra delay in trip- ping the internal current comparator. the two off-times average out to the required duty cycle to keep the output in regulation. there may be higher sw node jitter, apparent especially when synchronized to an external clock, but the output voltage ripple remains relatively small. fault conditions: current limiting and overvoltage the maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. in the ltc3876, the maximum sense voltage is controlled by the voltage on the v rng pin. with valley current mode control, the maximum sense voltage and the sense re-sistance determine the maximum allowed inductor valley current. the corresponding output current limit is: i limit = v sense(max) r sense + 1 2 ? i l the current limit value should be checked to ensure that i limit(min) > i out(max) . the current limit value should be greater than the inductor current required to produce maximum output power at the worst-case efficiency. applications information downloaded from: http:///
ltc3876 33 3876f worst-case efficiency typically occurs at the highest v in and highest ambient temperature. it is important to check for consistency between the assumed mosfet junction temperatures and the resulting value of i limit which heats the mosfet switches. to further limit current in the event of a short circuit to ground, the ltc3876 includes foldback current limiting. if the output falls by more than 50%, the maximum sense voltage is progressively lowered, to about one-fourth of its full value as the feedback voltage reaches 0v. a feedback voltage exceeding 7.5% for vddq channel 1 and 10% for vtt channel 2 of the regulated target of 0.6v is considered as overvoltage (ov). in such an ov condition, the top mosfet is immediately turned off and the bottom mosfet is turned on indefinitely until the ov condition is removed, i.e., the feedback voltage falling back below the threshold by more than a hysteresis of typical 15mv. current limiting is not active during an ov. if the ov persists, and the bg turns on for a longer time, the current through the inductor and the bottom mosfet may exceed their maximum ratings, sacrificing themselves to protect the load. opti-loop compensation opti-loop ? compensation, through the availability of the ith pin, allows the transient response to be optimized for a wide range of loads and output capacitors. the ith pin not only allows optimization of the control-loop behavior but also provides a dc-coupled and ac-filtered closed-loop response test point. the dc step, rise time and settling at this test point truly reflects the closed-loop response. assuming a predominantly 2nd order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the external series r ith -c ith1 filter at the ith pin sets the dominant pole-zero loop compensation. the values can be adjusted to optimize transient response once the final pcb layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected first because their various types and values determine the loop feedback factor gain and phase. an additional small capacitor, c ith2 , can be placed from the ith pin to sgnd to attenuate high frequency noise. note this c ith2 contributes an additional pole in the loop gain therefore can affect system stability if too large. it should be chosen so that the added pole is higher than the loop bandwidth by a significant margin. the regulator loop response can also be checked by looking at the load transient response. an output current pulse of 20% to 100% of full-load current having a rise time of 1s to 10s will produce v out and ith voltage transient-response waveforms that can give a sense of the overall loop stability without breaking the feedback loop. for a detailed explanation of opti-loop compensation, refer to application note 76. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to ? i load ? esr, where esr is the effective series resistance of c out . ? i load also begins to charge or discharge c out , generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. connecting a resistive load in series with a power mosfet, then placing the two directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condi- tion. the initial output voltage step resulting from the step change in load current may not be within the bandwidth of the feedback loop, so it cannot be used to determine phase margin. the output voltage settling behavior is more related to the stability of the closed-loop system. however, it is better to look at the filtered and compensated feedback loop response at the ith pin. the gain of the loop increases with the r ith and the band- width of the loop increases with decreasing c ith1 . if r ith is increased by the same factor that c ith1 is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. in addition, a feedforward capacitor, c ff , applications information downloaded from: http:///
ltc3876 34 3876f can be added to improve the high frequency response, as shown in figure 1. capacitor c ff provides phase lead by creating a high frequency zero with r fb2 which improves the phase margin. a more severe transient can be caused by switching in loads with large supply bypass capacitors. the discharged bypass capacitors of the load are effectively put in parallel with the converters c out , causing a rapid drop in v out . no regulator can deliver current quick enough to prevent this sudden step change in output voltage, if the switch connecting the c out to the load has low resistance and is driven quickly. the solution is to limit the turn-on speed of the load switch driver. hot swap? controllers are designed specifically for this purpose and usually incorporate current limiting, short-circuit protection and soft starting. load-release transient detection as the output voltage requirement of step-down switching regulators becomes lower, v in to v out step-down ratio increases, and load transients become faster, a major challenge is to limit the overshoot in v out during a fast load current drop, or load-release transient. inductor current slew rate di l /dt = v l /l is proportional to voltage across the inductor v l = v sw C v out . when the top mosfet is turned on, v l = v in C v out , inductor current ramps up. when bottom mosfet turns on, v l = v sw C v out = Cv out , inductor current ramps down. at very low v out , the low differential voltage, v l , across the inductor during the ramp down makes the slew rate of the inductor current much slower than needed to follow the load current change. the excess inductor current charges up the output capacitor, which causes overshoot at v out . if the bottom mosfet could be turned off during the load-release transient, the inductor current would flow through the body diode of the bottom mosfet, and the equation can be modified to include the bottom mosfet body diode drop to become v l = C(v out + v bd ). obviously the benefit increases as the output voltage gets lower, since v bd would increase the sum significantly, compared to a single v out only. the load-release overshoot at v out causes the error ampli- fier output, ith, to drop quickly. ith voltage is proportional to the inductor current setpoint. a load transient will result in a quick change of this load current setpoint, i.e., a negative spike of the first derivative of the ith voltage. the ltc3876 uses a detect transient (dtr) pin to monitor the first derivative of the ith voltage, and detect the load- release transient. referring to the functional diagram, the dtr pin is the input of a dtr comparator, and the internal reference voltage for the dtr comparator is half of intv cc . to use this pin for transient detection, ith compensation needs an additional r ith resistor tied to intv cc , and con- nects the junction point of ith compensation components c ith1 , r ith1 and r ith2 to the dtr pin as shown in the functional diagram. the dtr pin is now proportional to the first derivative of the inductor current setpoint, through the highpass filter of c ith1 and (r ith1 //r ith2 ). the two r ith resistors establish a voltage divider from intv cc to sgnd, and bias the dc voltage on dtr pin (at steady-state load or ith voltage) slightly above half of intv cc . compensation performance will be identical by using the same c ith1 and make r ith1 //r ith2 equal the r ith as used in conventional single resistor opti-loop compensation. this will also provide the r-c time constant needed for the dtr duration. the dtr sensitivity can be adjusted by the dc bias voltage difference between dtr and half intv cc . this difference could be set as low as 100mv, as long as the ith ripple voltage with dc load current does not trigger the dtr. when load current suddenly drops, v out overshoots, and ith drops quickly. the voltage on the dtr pin will also drop quickly, since it is coupled to the ith pin through a capacitor. if the load transient is fast enough that the dtr voltage drops below half of intv cc , a load release event is detected. the bottom gate (bg) will be turned off, so that the inductor current flows through the body diode in the bottom mosfet. this allows the sw node to drop below pgnd by a voltage of a forward-conducted silicon diode. this creates a more negative differential voltage (v sw C v out ) across the inductor, allowing the inductor current to drop at a faster rate to zero, therefore creating less overshoot on v out . applications information downloaded from: http:///
ltc3876 35 3876f the dtr comparator output is overridden by reverse inductor current detection (i rev ) and overvoltage (ov) condition. this means bg will be turned off when sense + is higher than sense C (i.e., inductor current is positive), as long as the ov condition is not present. when inductor current drops to zero and starts to reverse, bg will turn back on in forced continuous mode (e.g., the mode/ pllin pin tied to intv cc , or an input clock is present), even if dtr is still below half intv cc . this is to allow the inductor current to go negative to quickly pull down the v out overshoot. of course, if the mode/pllin pin is set to discontinuous mode (i.e., tied to sgnd), bg will stay off as inductor current reverse, as it would with the dtr feature disabled. note that it is expected that this dtr feature will cause additional loss on the bottom mosfet, due to its body diode conduction. the bottom fet temperature may be higher with a load of frequent and large load steps. this is an important design consideration. experiments on the demo board shows a 20c increase when a continuous 100% to 50% load step pulse train with 50% duty cycle and 100khz frequency is applied to the output. if not needed, this dtr feature can be disabled by tying the dtr pin to intv cc , or simply leave the dtr pin open so that an internal 2.5a current source will pull itself up to intv cc . efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percentage efficiency can be expressed as: %efficiency = 100% C (l1% + l2% + l3% + ...) where l1%, l2%, etc. are the individual losses as a per- centage of input power. although all dissipative elements in the circuit produce power losses, several main sources usually account for most of the losses in ltc3876 circuits: 1. i 2 r loss. these arise from the dc resistances of the mosfets, inductor, current sense resistor and is the ma- jority of power loss at high output currents. in continu- ous mode the average output current flows though the inductor l, but is chopped between the top and bottom mosfets. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the inductors dc resistances (dcr) and the board traces to obtain the i 2 r loss. for example, if each r ds(on) = 8m, r l = 5m, and r sense = 2m the loss will range from 15mw to 1.5w as the output current varies from 1a to 10a. this results in loss from 0.3% to 3% a 5v output, or 1% to 10% for a 1.5v output. efficiency varies as the inverse square of v out for the same external components and output power level. the combined effects of lower output voltages and higher currents load demands greater importance of this loss term in the switching regulator system. 2. transition loss. this loss mostly arises from the brief amount of time the top mosfet spends in the satura-tion (miller) region during switch node transitions. it depends upon the input voltage, load current, driver strength and mosfet capacitance, among other fac- tors, and can be significant at higher input voltages or higher switching frequencies. 3. drv cc current. this is the sum of the mosfet driver and intv cc control currents. the mosfet driver cur- rents result from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from drv cc to ground. the resulting dq/dt is a current out of drv cc that is typically much larger than the controller i q current. in continuous mode, i gatechg = f ? (qg (top) + qg (bot) ), where qg (top) and qg (bot) are the gate charges of the top and bottom mosfets, respectively. supplying drv cc power through extv cc could save several percents of efficiency, especially for high v in applications. connecting extv cc to an output-derived applications information downloaded from: http:///
ltc3876 36 3876f source will scale the v in current required for the driver and controller circuits by a factor of (duty cycle)/(ef- ficiency). for example, in a 20v to 5v application, 10ma of drv cc current results in approximately 2.5ma of v in current. this reduces the mid-current loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 4. c in loss. the input capacitor filters large square-wave input current drawn by the regulator into an averaged dc current from the supply. the capacitor itself has a zero average dc current, but square-wave-like ac current flows through it. therefore the input capacitor must have a very low esr to minimize the rms current loss on esr. it must also have sufficient capacitance to filter out the ac component of the input current to prevent additional rms losses in upstream cabling, fuses or batteries. the ltc3876 2-phase architecture improves the esr loss. hidden copper trace, fuse and battery resistance, even at dc current, can cause a significant amount of efficiency degradation, so it is important to consider them during the design phase. other losses, which include the c out esr loss, bottom mosfet s body diode reverse-recovery loss, and inductor core loss generally account for less than 2% additional loss. power losses in the switching regulator will reflect as a higher than ideal duty cycle, or a longer on-time for a constant frequency. this efficiency accounted on-time can be calculated as: t on t on(ideal) /efficiency when making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. if you make a change and the input current decreases, then the efficiency has increased. design example the following design example is the ddr3 application circuit as implemented on the standard ltc3876 qfn demo board 1631a. this dc/dc step-down converter design accommodates an input v in range of 4.5v to 14v, with a vddq output of 1.5v and a vtt output of 0.75v. the ddriii output channels are designed to produce 1.5v vddq at 20a, a 0.75v vtt 10a maximum average operat- ing current with a vtt reference output (vttr) capable of supplying up to 50ma. (see figure 11, ltc3876 demo circuit 1631a) the regulated channel 1 vddq output supply voltage is determined by: vddq = 0 . 6 v 1 + r fb 2 r fb 1 ?? ?? set vddq to 1.5v for ddriii application. using a 20k resistor for r fb1 , the resulting r bf2 is 30k. the regulated channel 2 vtt termination supply is differ- entially referenced to an internal resistor divider connected between the vddqsns and the v outsense C . the resulting differential vtt reference output (vttr) is one-half vddq which in this design example is 0.75v. the vtt termina- tion supply nominally regulates to 0.75v and will track any dynamic movement of the channel 1 vddq supply. the switching frequency for both channels is programmed by: r t k [] = 4 ? 41 5 50 fkhz [] C 2 . 2 for f = 400khz, r t = 102k. the minimum on-time occurs for maximum v in and should be greater than the typical minimum of 30ns with adequate margin. the minimum on-time margin should allow for device variability and the extension of effective on-time at light load due to the dead times. the reason for the on-time extension at light load is that the negative inductor current causes the switch node to rise which effectively adds to the on time. this is of limited concern to the channel 1 vddq but is of greater concern to the channel 2 vtt supply because it supplies significant negative current. for the ltc3876 the minimum on-time without any extension is 30ns, with driver dead times of 30ns. for strong negative currents in vtt the total dead time is the total of the minimum on-time, plus both dead times for 90ns. it is therefore recommended to keep the minimum on-time greater than 100ns for channel 2 vtt to assure pll lock under all operating conditions. applications information downloaded from: http:///
ltc3876 37 3876f the minimum on-time for channel 1 vddq is: t on(min) = v out v in(max) ?f = 1 . 5 v 14 v? 400 khz = 268 ns the minimum on-time for channel 2 vtt is: t on(min) = v out v in(max) ?f = 0 . 75 v 14 v? 400 khz = 134 ns set the channel 1 vddq inductor value l1 to give 35% ripple current at the maximum load to 20a for the maxi- mum v in of 14v using the adjusted operating frequency. l 1 = v out f ( ) i ripple ( ) 1 ? v out v in(max) = 1 . 5 v 400 khz ( ) 35 % t 20 a ( ) 1 ? 1 . 5 14 ?? ? ?? ? ?? ? ?? ? = 0 . 47 h set the channel 2 vtt inductor value l2 to give 35% ripple current at the maximum load to 10a for the maximum v in of 14v using the adjusted operating frequency. l 1 = v out f ( ) i ripple ( ) 1 ? v out v in(max) = 0 . 75 v 400 khz ( ) 37 . 5 % t 10 a ( ) 1 ? 0 . 75 14 = 0 . 47 h ?? ? ?? ? ?? ? ?? ? choose the nearest standard value of 0.47h for l2, which will result in 37.5% ripple current. the resulting channel 1 vddq maximum ripple current is: i l 1 = 1 . 5 v 400 khz ( ) 0 . 47 h ( ) 1 ? 1 . 5 v 14v = 7 . 12 a ?? ? ?? ? the resulting channel 2 vtt maximum ripple current is: i l 2 = 0 . 75 v 400 khz ( ) 0 . 47 h ( ) 1 ? 0 . 75 v 14 v = 3 . 78 a ?? ? ?? ? for figure 11, standard demo board the current limit is set using sense resistors. the v rng is grounded which results in a maximum v sense voltage across the r sense resistor of 30mv. if we assume 50% over the nominal output of 20a this gives a starting point of 1m for channel 1 vddq and 2m for channel 2 vtt. channel 1 vddq current limit for 1m r sense . ilimit vddq = v sense r sense + i l 2 = 30 mv 1 m + 7 . 12 a 2 = 33 . 5 a channel 2 vtt current limit for 2m r sense . ilimit vtt = v sense r sense + i l 2 = 30 mv 2 m + 3 . 78 a 2 = 16 . 9 a in high power applications, dcr current sensing is often preferred to r sense in order to maximize efficiency. the inductor model is selected based on its inductor and dcr value. the wrth we7443330047 with a rated current of 20a, a saturation current of 47a and dcr of 0.8m is chosen for channel 1 vddq. the wrth we7443340047 with a rated current of 19a, a saturation current of 32a and dcr of 1.72m is chosen for channel 2 vtt. the dcr demo board design is figure 13. in this design example v rng was grounded to produce an internal default value of 30mv on v sense . channel 1 vddq dcr current limit: ilimit vddq = v sense r sense + i l 2 = 30mv 0.8m ?(1+(100 cC25 c)? 0.4% / c) + 7.12a 2 =32.4a channel 2 vtt dcr current limit: ilimit vtt = v sense r sense + il 2 = 30mv 1.72m ?(1+(100 cC25 c)? 0.4% / c) + 3 .78a 2 = 15.3a applications information downloaded from: http:///
ltc3876 38 3876f the dcr sense filter is designed using a simple rc filter across the inductor. if the inductor value and dcr is known, choose a sense filter c and calculate filter resistance. channel 1 dcr filter resistor r dcr1 : r dcr 1 = l 1 dcr ?c dcr = 0 . 47 h 0 . 8 m ? 0 . 1 f = 5 . 9 k channel 2 dcr filter resistor r dcr2 : r dcr 1 = l 1 dcr ?c dcr = 0 . 47 h 1 . 72 m ? 0 . 1 f = 2 . 74 k the external n-channel mosfets are chosen based on current capability and efficiency. the renesas rjk0305dbp (r ds(on) = 13m(maximum), c miller = 150pf, vgs = 4.5v, v miller = 3v, ja = 40c/w, t j(max) = 150c) is chosen for the top mosfet (main switch). the renesas rjk0330dbp (r ds(on) = 3.9m(maximum), v gs = 4.5v, ja = 40c/w, t j(max) =150c) is chosen for the bottom mosfet (synchronous switch).the power dissipation for each mosfet can be calculated for v in = 14v and typical t j =125c. the power dissipation for v in = 14v and t j =125c for the top mosfet is: p top = 1 . 5 v 14 v 20 a 2 1 + 0 . 4% 125 cC 25 c 0 . 013 + 14 v 2 20 a 2 150 pf 2 . 5 5 . 3 vC 3 v + 1 . 2 3 v ?? ? ?? ? ?? ? ?? ? 400 khz = 0 . 78 w + 0 . 17 w = 0 . 95 w ( ) ( ) ( ) ( ) ( ) ( ) ( ) the power dissipation for v in = 14v and t j =125c for 2x bottom mosfets is: p bot = 14 vC 1 . 5 v 14 v 20 a 2 x 2 1 + 0 . 4 % 125 cC 25 c 0 . 0039 = 0 . 4875 w ?? ? ?? ? ( ) ( ) ( ) the resulting junction temperatures for ambient tempera-ture t a = 75c are: t j(top) = 75c + (0.95w)(40c/w) = 113c t j(bot) = 75c + (0.975w)(40c/w) = 94.5c these numbers show that careful attention should be paid to proper heat sinking when operating at higher ambient temperatures. select c in capacitors to give ample capacitance and rms ripple current rating. consider worst-case duty cycles per figure 6. if operated at steady-state with sw nodes fully interleaved, the two channels would generate not more than 7.5a rms at full load. in this design example, 2x 10f 25v x5r ceramic capacitors are put in parallel to take the rms ripple current with 330f aluminum electrolytic bulk capacitors for stability. for 10f 1210 x5r ceramic capacitors, try to keep the ripple current less than 3a rms through each device. the bulk capacitor is chosen for rms rating per simulation with the circuit model provided. the power supply output capacitors c out are chosen for a low esr. for channel 1 vddq, the output capacitor sanyo 2r5tpe330m9, has an esr of 9m which results in 4.5m for two in parallel. for channel 2 vtt, the output capacitor sanyo 2r5tpe330m9, has an esr of 9m. the output ripple for each channel is given as: vddq(ripple) = i l(max) (esr) = (7.12a) ? (4.5m) = 32mv vtt(ripple) = i l(max) (esr) = (3.78a) ? (9m) = 34mv a 0a to 10a load step in vddq will cause an output change of up to: vddq(step) = i load (esr) = 10a ? 0.0045m = 45mv a 0a to 5a load step in vtt will cause an output change of up to: vtt(step) = i load (esr) = 5a ? 0.009m = 45mv optional 100f ceramic output capacitors are included to minimize the effect of esl in the output ripple and to improve load step response. applications information downloaded from: http:///
ltc3876 39 3876f pcb layout checklist the printed circuit board layout is illustrated graphically in figure 12. use the following checklist to ensure proper operation of the ltc3876: ? a multilayer printed circuit board with dedicated ground planes is generally preferred to reduce noise coupling and improve heat sinking. the ground plane layer should be immediately next to the routing layer for the power components, e.g., mosfets, inductors, sense resistors, input and output capacitors etc. ? keep sgnd and pgnd separate. upon finishing the layout, connect sgnd and pgnd together with a single pcb trace underneath the ic from the sgnd pin through the exposed pgnd pad to the pgnd pin. ? all power train components should be referenced to pgnd; all components connected to noise-sensitive pins, e.g., ith, rt , track/ss and v rng , should return to the sgnd pin. keep pgnd ample, but sgnd area compact. use a modified star ground technique: a low impedance, large copper area central pcb point on the same side of the as the input and output capacitors. ? place power components, such as c in , c out , mosfets, d b and inductors, in one compact area. use wide but shortest possible traces for high current paths (e.g., v in , v out , pgnd etc.) to this area to minimize copper loss. ? keep the switch nodes (sw1,2), top gates (tg1,2) and boost nodes (boost1,2) away from noise-sensitive small-signal nodes, especially from the opposite channels voltage and current sensing feedback pins. these nodes have very large and fast moving signals and therefore should be kept on the output side of the ltc3876 (power-related pins are toward the right hand side of the ic), and occupy minimum pc trace area. use compact switch node (sw) planes to improve cooling of the mosfets and to keep emi down. if dcr sensing is used, place the top filter resistor (r1 only in figure 5) close to the switch node. ? the top n-channel mosfets of the two channels have to be located within a short distance from (preferably <1cm) each other with a common drain connection at c in . do not attempt to split the input decoupling for the two channels as it can result in a large resonant loop. ? connect the input capacitor(s), c in , close to the power mosfets. this capacitor provides the mosfet transient spike current. connect the drain of the top mosfet as close as possible to the (+) plate of the ceramic portion of input capacitors c in . connect the source of the bot- tom mosfet as close as possible to the (C) terminal of the same ceramic c in capacitor(s). these ceramic capacitor(s) bypass the high di/dt current locally, and both top and bottom mosfet should have short pcb trace lengths to minimize high frequency emi and prevent mosfet voltage stress from inductive ringing. ? the path formed by the top and bottom n-channel mosfets, and the c in capacitors should have short leads and pcb trace. the (C) terminal of output capaci-tors should be connected close to the (C) terminal of c in , but away from the loop described above. this is to achieve an effect of kevin (4-wire) connection to the input ground so that the chopped switching current will not flow through the path between the input ground and the output ground, and cause common mode output voltage ripple. ? several smaller sized ceramic output capacitors, c out , can be placed close to the sense resistors and before the rest bulk output capacitors. ? the filter capacitor between the sense + and sense C pins should always be as close as possible to these pins. ensure accurate current sensing with kevin (4-wire) connections to the soldering pads from underneath the sense resistors or inductor. a pair of sense traces should be routed together with minimum spacing. r sense , if used, should be connected to the inductor on the noiseless output side, and its filter resistors close to the sense + /sense C pins. for dcr sensing, however, filter resistor should be placed close to the inductor, and away from the sense + /sense C pins, as its terminal is the sw node. applications information downloaded from: http:///
ltc3876 40 3876f applications information figure 11. design example: 4.5v to 14v input, vddq 1.5v/20a and vtt 0.75v/10a output, 400khz, dcr, step-down converter ? keep small-signal components connected noise-sensi- tive pins (give priority to sense + /sense C , v outsense1 + / v outsense1 C , v fb2 , rt , ith, v rng pins) on the left hand side of the ic as close to their respective pins as pos-sible. this minimizes the possibility of noise coupling into these pins. if the ltc3876 can be placed on the bottom side of a multilayer board, use ground planes to isolate from the major power components on the top side of the board, and prevent noise coupling to noise sensitive components on the bottom side. 13.7k 3876 f11a 0.1f 0.1f 1f 470pf c in1 : sanyo 16svp180m c in2: murata grm32dr61e106ka12l c out2 ,c out4 : sanyo 2r5tpe330m9 c out1 , c out3 : murata grm31cr60j107me39l db1, db2: central semi cmdsh-3 l1: wrth 7443330047 l2: wrth 7443340047 mt1, mb2: infineon bsc0901ns mb1: infineon bsc010ne2ls mt2: infineon bsc050ne2ls 4700pf l1 0.47h c out3 100f c out4 330f vtt0.75v 10a db2 mt2mb2 ltc3876 2.2 2.2 30.1k vttr 50ma 1 100k 12.7k 100k v in 1f 0.1f 4.7f 0.1f 0.01f 120pf 1500pf l1 0.47h c out2 330fw 2 c out1 100f vddq 1.5v 20a v in 4.5v to 14v 20k sense1 C sense1 + boost1tg1 sw1 sense2 + boost2 tg2 sw2 drv cc1 intv cc drv cc2 extv cc db1 mt1 5.9k 2.74k sense2 C bg1 bg2 vttrvcc pgndv outsense1 + vddqsnsv outsense1 C pgood vttr vttsns track/ss1ith1 dtr1 v rng1 ith2 cvcc phasmd mode/pllin clkout v rng2 sgndrun rt pgood mb1 1f c in2 10fw 3 c in1 180fw 2 2.2f load current (a) 0.1 efficiency (%) power loss (w) 90 100 11 0 3876 f11b 6050 40 8070 4.0 4.5 1.50.5 1.00 3.0 3.52.5 2.0 forcedcontinuous mode discontinuousmode v in = 12v v ddq = 1.5v downloaded from: http:///
ltc3876 41 3876f applications information figure 12. recommended pcb layout diagram ? place the resistor feedback divider r fb1 , r fb2 close to v outsense1 + and v outsense1 C pins for channel 1, or v fb2 pin for channel 2, so that the feedback voltage tapped from the resistor divider will not be disturbed by noise sources. route remote sense pcb traces (use a pair of wires closely together for differential sensing in channel 1) directly to the terminals of output capacitors for best output regulation. ? place decoupling capacitors c ith2 next to the ith and sgnd pins with short, direct trace connections. ? use sufficient isolation when routing a clock signal into the mode/pllin pin or out of the clkout pin, so that the clock does not couple into sensitive pins. ? place the ceramic decoupling capacitor c intvcc between the intv cc pin and sgnd and as close as possible to the ic. ? place the ceramic decoupling capacitor c drvcc close to the ic, between the combined drv cc1,2 pins and pgnd. ? filter the v in input to the ltc3876 with an rc filter. place the filter capacitor close to the v in pin. ? if vias have to be used, use immediate vias to connect components to the sgnd and pgnd planes of ltc3876. use multiple large vias for power components. sense2 C ltc3876 sense2 + vttsns ith2 c ith1(2) c ith2(2) localized sgnd trace pgood2 boost2 tg2 c b2 d b2 d b1 r intvcc sw2 drv cc2 extv cc v in drv cc1 bg1 sw1 tg1 boost1 pgood1 run1 dtr1 pgnd intv cc c vcc bg2 c intvcc c vin r vin c drvcc c b1 c in ceramic ceramic mt2 mb2 mt1 mb1 + v in l2 l1 c out2 v out2 gnd v out1 + c out1 + r sense1 3876 f12 r sense2 rt r t v rng2 phasmdmode/pllin clkout sgnd v rng1 r ith1(2) c ith2(1) c ith1(1) c ss1 r fb1(1) r ith1(1) ith1track/ss1 v outsense1 + v outsense1 C sense1 + sense1 C r ith2(1) r fb2(1) downloaded from: http:///
ltc3876 42 3876f applications information ? flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power components. connect the copper areas to dc rails only, e.g., pgnd. pcb layout debugging only after each controller is checked for its individual performance should both controllers be turned on at the same time. it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit. monitor the output switching node (sw pin) to synchronize the oscilloscope to the internal oscillator output clkout, or external clock if used. probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the application. the frequency of operation should be maintained over the input voltage range. the phase should be maintained from cycle to cycle in a well designed, low noise pcb implementation. variation in the phase of sw node pulse can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. overcompensa- tion of the loop can be used to tame a poor pcb layout if regulator bandwidth optimization is not required. a particularly difficult region of operation is when one controller channel is turning on (right after its current comparator trip point) while the other channel is turning off its top mosfet at the end of its on-time. this may cause minor phase-lock jitter at either channel due to noise coupling. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the un- dervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher out- put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages, look for inductive coupling between c in , top and bottom mosfet components to the sensitive current and voltage sensing traces. in addition, investigate common ground path voltage pickup between these components and the sgnd pin of the ic. high switching frequency operation at high switching frequencies there may be an increased sensitivity to noise. special care may need to be taken to prevent cycle-by-cycle instability and/or phase-lock jitter. first, carefully follow the recommended layout techniques to reduce coupling from the high switching voltage/current traces. additionally, use low esr and low impedance x5r or x7r ceramic input capacitors: up to 5f per amp. of load current may be needed. if necessary, increase ripple sense voltage by increasing sense resistance value and v rng setting, to improve noise immunity. downloaded from: http:///
ltc3876 43 3876f applications information figure 13. 4.5v to 14v input, vddq 1.8v/20a and vtt 0.9v/10a output, 400khz, dcr, step-down converter 13.7k 3876 f13a 0.1f 0.1f 1f 470pf 4700pf l1 0.47h c out3 100f c out4 330f vtt0.9v 10a db2 mt2mb2 ltc3876 2.2 2.2 30.1k vttr 50ma 1 100k 12.7k 100k v in 1f 0.1f 4.7f 0.1f 0.01f 120pf 1500pf l1 0.47h c out2 330fw 2 c out1 100f vddq 1.8v 20a v in 4.5v to 14v 20k sense1 C sense1 + boost1tg1 sw1 sense2 + boost2 tg2 sw2 drv cc1 intv cc drv cc2 extv cc db1 mt1 5.9k 2.74k sense2 C bg1 bg2 vttrvcc pgndv outsense1 + vddqsnsv outsense1 C pgood vttr vttsns track/ss1ith1 dtr1 v rng1 ith2 cvcc phasmd mode/pllin clkout v rng2 sgndrun rt pgood mb1 1f c in2 10fw 3 c in1 180fw 2 2.2f c in1 : sanyo 16svp180m c in2 : murata grm32dr61e106ka12l c out2 ,c out4 : sanyo 2r5tpe330m9 c out1 , c out3 : murata grm31cr60j107me39l db1, db2: central semi cmdsh-3 l1: wrth 7443330047 l2: wrth 7443340047 mt1, mb2: infineon bsc0901ns mb1: infineon bsc010ne2ls mt2: infineon bsc050ne2ls load current (a) 0.1 efficiency (%) power loss (w) 90 100 11 0 3876 f13b 6050 40 8070 4.0 4.5 1.50.5 1.00 3.0 3.52.5 2.0 forcedcontinuous mode discontinuousmode v in = 12v vddq = 1.8v downloaded from: http:///
ltc3876 44 3876f figure 14. 4.5v to 28v input, vddq 1v/20a and vtt 0.50v/10a output, 200khz, r sense , step-down converter applications information 2.55k 3876 f14a 1nf 0.1f 1f 1000pf 2700pf l2 0.68h c out3 100f c out4 330f vtt0.5v 10a 100100 db2 mt2mb2 r32 0.003 ltc3876 2.2 2.2 30.1k vttr 50ma 1 100k 18.2k 205k 113k20k v in 1f 1nf 4.7f 0.1f 0.1f 220pf 220pf l1 0.67h c out2 330fw 2 c out1 100f vddq 1v 20a v in 4.5v to 28v 100100 20k sense1 C sense1 + boost1tg1 sw1 sense2 + boost2 tg2 sw2 drv cc1 intv cc drv cc2 extv cc db1 mt1 0.002 r31 sense2 C bg1 bg2 vttrvcc pgndv outsense1 + vddqsnsv outsense1 C pgood vttr vttsns track/ss1ith1 dtr1 v rng1 ith2 cvcc phasmd mode/pllin clkout v rng2 sgndrun rt pgood mb1 1f c in2 10fw 3 c in1 100f 2.2f c in1 : nichicon ucj1h101mcl1gs c in2 : murata grm32er71h106k c out2 ,c out4 : sanyo 2r5tpe330m9 c out1 , c out3 : murata grm31cr60j107me39l db1, db2: central semi cmdsh-3 l1: wrth 744315067 l2: wrth 744311068 mt1: infineon bsc035n04ls mb1, mb2: infineon bsc011n03ls mt2: vishay sir462dp load current (a) 0.1 efficiency (%) power loss (w) 90 100 11 0 3876 f14b 6050 40 8070 4.0 1.50.5 1.00 3.0 3.52.5 2.0 forcedcontinuous mode discontinuousmode v in = 12v vddq = 1v downloaded from: http:///
ltc3876 45 3876f figure 15. 4.5v to 38v input, vddq 1.2v/20a and vtt 0.60v/10a output, 200khz, r sense , step-down converter applications information 4.22k 3876 f15a 1nf 0.1f 1f 560pf 1800pf l2 0.82h c out3 100f c out4 330fw 2 vtt0.6v 10a db2 mt2mb2 ltc3876 2.2 r31 0.002 2.2 20k vttr 50ma 1 100k 13.7k 86.6k 118k v in 1f 1nf 4.7f 0.1f 0.01f 180pf 560pf c out2 330fw 4 c out1 100f vddq 1.2v 20a v in 4.5v to 38v 20k sense1 C sense1 + boost1tg1 sw1 sense2 + boost2 tg2 sw2 drv cc1 intv cc drv cc2 extv cc db1 mt1 r32 0.002 sense2 C bg1 bg2 vttrvcc pgndv outsense1 + vddqsnsv outsense1 C pgood vttr vttsns track/ss1ith1 dtr1 v rng1 ith2 cvcc phasmd mode/pllin clkout v rng2 sgndrun rt pgood mb1 l1 0.82h 1f c in2 10fw 4 c in1 100f 2.2f c in1 : nichicon ucj1h101mcl1gs c in3 , c in4 , c in5 : murata grm32er71h106k c out1 , c out2 , c out5 : sanyo 2r5tpe330m9 c out4 , c out7 : murata grm31cr60j107me39l db1, db2: central semi cmdsh-3 l1: wrth 744315067 l2: wrth 744311068 mt1: infineon bsc035n04ls mb1 mb2: infineon bsc011n03ls mt2: vishay sir462dp 2.49 1.15 load current (a) 0.1 efficiency (%) power loss (w) 90 100 11 0 3876 f15b 6050 40 8070 5.04.0 4.5 1.50.5 1.00 3.0 3.52.5 2.0 forcedcontinuous mode discontinuousmode v in = 12v vddq = 1.2v downloaded from: http:///
ltc3876 46 3876f 5.00 p 0.10 note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1top mark (see note 6) 37 12 38 bottom viewexposed pad 5.50 ref 5.15 0.10 7.00 p 0.10 0.75 p 0.05 r = 0.125 typ r = 0.10 typ 0.25 p 0.05 (uh) qfn ref c 1107 0.50 bsc 0.200 ref 0.00 C 0.05 recommended solder pad layout apply solder mask to areas that are not soldered 3.00 ref 3.15 0.10 0.40 p 0.10 0.70 p 0.05 0.50 bsc 5.5 ref 3.00 ref 3.15 0.05 4.10 p 0.05 5.50 p 0.05 5.15 0.05 6.10 p 0.05 7.50 p 0.05 0.25 p 0.05 packageoutline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notchr = 0.30 typ or 0.35 s 45 o chamfer uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701 rev c) package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. downloaded from: http:///
ltc3876 47 3876f 4.75 (.187) ref fe38 (aa) tssop rev c 0910 0.09 C 0.20 (.0035 C .0079) 0 s C 8 s 0.25 ref 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 1 19 20 ref 9.60 C 9.80* (.378 C .386) 38 1.20 (.047) max 0.05 C 0.15 (.002 C .006) 0.50 (.0196) bsc 0.17 C 0.27 (.0067 C .0106) typ recommended solder pad layout 0.315 0.05 0.50 bsc 4.50 ref 6.60 0.10 1.05 0.10 4.75 ref 2.74 ref 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note:1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 38-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1772 rev c) exposed pad variation aa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. downloaded from: http:///
ltc3876 48 3876f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2011 lt 1111 printed in usa typical application 4.5v to 5.5v input, vddq 1.5v/20a and vtt 0.75v/10a output, 1.2mhz, r sense , step-down converter part number description comments ltc3776 dual, 2-phase, no r sense ?, synchronous controller for ddr/qdr memory termination 2.75v v in 9.8v, v out tracks one-half v ref , 4mm 4mm qfn-24, ssop-24 ltc3717 high power ddr memory termination regulator 4v v in 36v, v out tracks one-half v in or v ref ltc3718 bus termination supply for low voltage v in 1.5v v in , supplies 5v gate drive for n-channel mosfets ltc3831 high power ddr memory termination regulator v out tracks one-half v in or v ref , 3v v in 8v ltc3413 3a monolithic ddr memory termination regulator 2.25v v in 5.5v, tssop-16e ltc3833 fast controller on-time, high frequency synchronous step-down controller with diff amp up to 2mhz operating frequency 4.5v < v in < 38v, 0.6v < v out < 5.5v, 3mm 4mm qfn-20, tssop-20e ltc3838 dual, fast, accurate step-down dc/dc controller with differential output sensing up to 2mhz operating frequency 4.5v < v in < 38v, 0.6v < v out < 5.5v, 5mm 7mm qfn-38, tssop-38e ltc3634 15v dual 3a monolithic ddr memory termination 3.6v v in 15v, 4mm 5mm qfn-28, tssop-28e ltc3617 6a monolithic ddr memory termination 2.25v v in 5.5v, 3mm 5mm qfn-24 ltc3618 dual 3a monolithic ddr memory termination 2.25v v in 5.5v, 4mm 4mm qfn-24, tssop-24 related parts 33.2k 3876 ta02 1nf 0.1f 1f 120pf 270pf l2 0.22h c out3 100f c out4 330f vtt0.75a 10a 100100 db2 mt2mb2 r32 0.003 ltc3876 2.2 2.2 30.1k vttr 50ma 1 100k 68.1k 32.4k v in 1f 1nf 4.7f 0.1f 0.01f 39pf 150pf l1 0.18h c out2 330fw 2 c out1 100f vddq 1.5v 20a v in 4.5v to 5.5v 100100 20k sense1 C sense1 + boost1tg1 sw1 sense2 + boost2 tg2 sw2 drv cc1 intv cc drv cc2 extv cc v in db1 mt1 r31 0.002 sense2 C bg1 bg2 vttrvcc pgndv outsense1 + vddqsnsv outsense1 C pgood vttr vttsns track/ss1ith1 dtr1 v rng1 ith2 cvcc phasmd mode/pllin clkout v rng2 sgndrun rt pgood mb1 1f c in2 10fw 3 c in1 180f 2.2f c in1 : sanyo 16svp180m c in2 : murata grm32dr61e106ka12l c out2 , c out4 : sanyo 2r5tpe330m9 c out1 , c out3 : murata grm31cr60j107me39l db1, db2: central semi cmdsh-3 l1: toko fcul1040-h-r18m l2: toko fdue0640-r22m mt1, mb1, mb2:infineon bsc0901ns mt2: infineon bsc050ne2ls 649 downloaded from: http:///

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